Gotta throw in something, in spite of headache.
First, the obvious:
-The different location of the temp probe will return different data, but as long as the same setup is used, block differential performance can be determined, to some extent.
-While it would be nice to get raw data temperature measurements (core side) that match what an actual processor would report (actual or interpreted through BIOS), it is unfortunately rarely possible. What is possible though, is to add a correction that would simulate the actual core temp, as reported by BIOS/MBM or other/or directly through the CPU diode, the last of which is neither obvious nor practical, the firsts of which is racked with issues.
Then the not so obvious
-The TTV issue. what I see is a claim (which I'll support) that measuring the core side temp by measuring the temp of the IHS, is flawed. But if the claim extends to state that the block contact area may be affected by an IHS, and by extension, using an IHS temp measurement alongside, then I would submit that the issue is with the block design, not the TTV/IHS.
-It really isn't practical to measure the IHS temp, because it involves altering the DUT (Device Under Test), and it may not always be possible to alter a DUT in that way (i.e. cutting a groove on the contact area, to route a temp probe to the middle). I will stand against altering a block, for the sake of measuring performance. While the term may be applied wrongly, I'll dub it "destructive testing".
-Apogee claims: I share many's opinions that the Apogee design, as presented, regardless of the inlet geometry, cannot possibly match the performance of the Storm block, unless the design of Storm was altered from the G4/G5 original in an unfavorable way.
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