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Originally Posted by Brians256
Les, thanks for running the numbers to show how a centered power source distributes heat across a 101mm^2 silicon die (I hope I'm reading your graphs correctly).
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No, you are not understanding correctly.The graphs are illustrative statements of the problem. The graphs are "suggested heat sources" not the distribution.
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Originally Posted by Brians256
I'm not sure how they can help, though. We don't have a case of even a single hot spot. A P4 die has several potential hot spots that shift as the instruction mix changes.
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Two illustrative HotSpots on the "pkg-face" of the same die are shown (
link)
Helps because a statement of the problem is essential to getting a solution.The distribution is part of the solution. The solution is being investigated, starting with an even simpler case than previously illustrated - Uniform Central HotSpot on square 0.5mm thick slice of Si(attachment)
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Originally Posted by Brians256
Would a waterblock do significantly better if it was designed to focus on known hotspots of a particular CPU? Better, meaning better overclock or increased stability (e.g. better stability despite equal or worse/higher temperatures measured at some arbitrary location like the P4 diode)?
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Dunno, but AMD engineers are giving due consideration(
"Beware of Hot Spots" Marci's link)