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General Liquid/Water Cooling Discussion For discussion about Full Cooling System kits, or general cooling topics. Keep specific cooling items like pumps, radiators, etc... in their specific forums.

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Unread 11-21-2005, 01:33 PM   #176
Les
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Quote:
Originally Posted by unregistered
TTV data passing Cathar ?
Ah! The laws of physics.
Would be nice, if he would illustrate, with fictitious values, where the laws are broken . The "large blue (3,2 0.0039) point", for h(eff)= 270,000w/m^2*c on 14.4x14.4x1mm, breaks no laws(Post133)

Quote:
Originally Posted by Orkan
Considering most in the industry go to bill for block testing... If he tells me that stephen @ swiftech is doing the tests, and says stephen is as good or better than he is... I'll buy the data. I seriously doubt it will be disproved, on the AMD X2 platform w/IHS anyway.
Must be wrong
You are being logical (jk)
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Unread 11-21-2005, 01:56 PM   #177
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"Considering most in the industry go to bill for block testing"

i was under the impreshon ph did all the well trusted data ? as from what i see from a lot of post round hear billa's obsesshon with swiftech is takeing on an eaven more bitter taste with evrything being related to them aparantly being 100x better than nething elce infact evrthing elce is a copy of what swiftech make/have made

and then he speeks of fan boys


i persoanly will be waiting for a non biased test
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Unread 11-21-2005, 02:03 PM   #178
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Gotta throw in something, in spite of headache.

First, the obvious:
-The different location of the temp probe will return different data, but as long as the same setup is used, block differential performance can be determined, to some extent.

-While it would be nice to get raw data temperature measurements (core side) that match what an actual processor would report (actual or interpreted through BIOS), it is unfortunately rarely possible. What is possible though, is to add a correction that would simulate the actual core temp, as reported by BIOS/MBM or other/or directly through the CPU diode, the last of which is neither obvious nor practical, the firsts of which is racked with issues.

Then the not so obvious
-The TTV issue. what I see is a claim (which I'll support) that measuring the core side temp by measuring the temp of the IHS, is flawed. But if the claim extends to state that the block contact area may be affected by an IHS, and by extension, using an IHS temp measurement alongside, then I would submit that the issue is with the block design, not the TTV/IHS.

-It really isn't practical to measure the IHS temp, because it involves altering the DUT (Device Under Test), and it may not always be possible to alter a DUT in that way (i.e. cutting a groove on the contact area, to route a temp probe to the middle). I will stand against altering a block, for the sake of measuring performance. While the term may be applied wrongly, I'll dub it "destructive testing".

-Apogee claims: I share many's opinions that the Apogee design, as presented, regardless of the inlet geometry, cannot possibly match the performance of the Storm block, unless the design of Storm was altered from the G4/G5 original in an unfavorable way.
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Unread 11-21-2005, 02:05 PM   #179
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fl
your summation of your understanding is concise

Ben
consider the MCW55 data, now thin the bp; what would you expect ?
or is the MCW55 data flawed because it cools the IHS clad heat source effectively also ? (is that not the goal ?)

it is strange that no one wishes to consider that other data except Les (who is omnivorous)

Last edited by BillA; 11-21-2005 at 02:20 PM.
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Unread 11-21-2005, 02:11 PM   #180
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tnx love you 2
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Unread 11-21-2005, 02:18 PM   #181
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Someone remind me if the Intel TTV uses an actual processor, or that crazy ~2" diameter heater element.
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Unread 11-21-2005, 02:26 PM   #182
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sort of like a processor?

http://developer.intel.com/design/Pe...s/30056401.pdf

Appendix E
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Unread 11-21-2005, 02:32 PM   #183
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Quote:
Originally Posted by bigben2k
Someone remind me if the Intel TTV uses an actual processor, or that crazy ~2" diameter heater element.
post #173
both guesses are wrong, treat it as a 'black box' designed for its purpose
answer your own question: why would an exaggerated heat source size be used ? (again, consider the purpose for the heat source)

Orkan
old version/setup, but generally similar
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Unread 11-21-2005, 02:36 PM   #184
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Quote:
Originally Posted by unregistered
...
consider the MCW55 data, now thin the bp; what would you expect ?
or is the MCW55 data flawed because it cools the IHS clad heat source effectively also ? (is that not the goal ?)...
-From a designer perspective (i.e. reticular implant), I would expect different performance, but it could go either way. Too thin a bp could be detrimental. Optimal thickness would be better, but specific to a flow rate.

To quote the textbook:
Quote:
The TTV provides a well characterized tool suitable for simulating processor thermal behavior well before actual parts are available. A resistance-type heater band covers the surface area of the test die and is used to
simulate the heat generation of an actual processor core. The power dissipation is uniform across the test die and requires correction factors to account for non-uniform heat dissipation in an actual processor.
TTV fuzzyland all over again.

Code:
Thermal Characterization Parameter 	Correction factor using IntelĀ® PentiumĀ® 4 Processor on 90 nm Process TTV
ΨCS 	1.103
ΨSA 	1.006
ΨCA 	1.030
This data shows promise of an actual replication of a core. Is it so?

Ok will go with "blackbox".
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Unread 11-21-2005, 02:52 PM   #185
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Holy smokes; just realized that the proposed groove for thermocouple routing is IN the IHS (page 68).
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Unread 11-21-2005, 03:12 PM   #186
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welcome to the party Ben
so a tester will groove the CPU used as a heat source/overclocking basis and bond in a 40ga TC,
not a die temp but perfectly usable (the scale will be compressed compared to the silicon temp)

EDIT
it just occured to me,
do you guys understand that the Intel thermal limits are based on the case (IHS) temp ?

this die temp stuff is not necessary to effective cooling as such is a consideration in package design, for thermal mgmt Intel defines the case temp as the basis of many calcs (AMD grooves the sink so their reference is the other side of the TIM joint, the sink or wb bp - probably a relic of their bare die days)

Last edited by BillA; 11-21-2005 at 03:25 PM.
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Unread 11-21-2005, 03:30 PM   #187
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I have described an acceptable IHS heat die setup multiple times. Seems some people are too busy hanging shit to notice it.

I've gone beyond the point of caring now. Snide asshat comments have destroyed for me any illusion that I was talking with people who have anything less than a politically oriented motivation for their comments.

I'm out. Totally.
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Unread 11-21-2005, 03:42 PM   #188
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Quote:
Originally Posted by unregistered
welcome to the party Ben...
I've arrived!

Ran a quick cal of the 85% uniformity JEDEC requirement; all is well, from a contact area perspective (96% contact over core area, based on 14mm square core).

Quote:
EDIT
it just occured to me,
do you guys understand that the Intel thermal limits are based on the case (IHS) temp ?
I did. Worst case too, which gives us overclockeability.

Quote:
this die temp stuff is not necessary to effective cooling as such is a consideration in package design, for thermal mgmt Intel defines the case temp as the basis of many calcs (AMD grooves the sink so their reference is the other side of the TIM joint, the sink or wb bp - probably a relic of their bare die days)
Agreed, AMD needs to catch up.

Quote:
Originally Posted by Cathar
...
I'm out. Totally.
Ah darn, now I have to pickup Stew's case (no irony, will actually do).

Later today.
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Unread 11-21-2005, 03:44 PM   #189
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Quote:
Originally Posted by bigben2k
Ah darn, now I have to pickup Stew's case.
I wouldn't bother. Just wait for independent test data.

Will be interesting to see the fallout when that occurs, whichever way the cards fall.
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Unread 11-21-2005, 03:58 PM   #190
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Quote:
Originally Posted by Les
Ah! The laws of physics.
Would be nice, if he would illustrate, with fictitious values, where the laws are broken . The "large blue (3,2 0.0039) point", for h(eff)= 270,000w/m^2*c on 14.4x14.4x1mm, breaks no laws(Post133)
Was referring to data that you know that I don't have the permission to publish.

You always knew that though. Too busy constructing snide comments it seems.

Said data projected a unit thermal resistance lower than that of the inherent thermal spreading resistance of the copper in the unit.

Just wanted to make that point clear before leaving this.
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Unread 11-21-2005, 04:18 PM   #191
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Quote:
Originally Posted by Cathar
I wouldn't bother. Just wait for independent test data.

Will be interesting to see the fallout when that occurs, whichever way the cards fall.
agreed, no hard feelings - its about testing
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Unread 11-21-2005, 05:05 PM   #192
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At the end of the day... I doubt switching from apogee to storm, or storm to apogee would grant one a higher overclock.

Independent testing? ... ... ...

A forum full of people that are considered industry experts can't even come to a conclusion about how to test a block correctly.

So who is going to do this "independent testing?" Hell... maybe I'll buy a block for them so they can put this crap to rest.
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Last edited by Orkan; 11-21-2005 at 05:17 PM.
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Unread 11-21-2005, 05:27 PM   #193
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Orkan, as much of us like to bitch and moan about things like testing, it is difficult to do properly... there are only about 5 such people that can do it right for the most part. We are indeed splitting hairs here, but why not I hope pHaestus will indeed do some tests, although by the tone of his post(s) it doesn't seem promising. I think Lee (robotech) will do a test and then hopefully JoeC (although, his data can be whacked). If we get 3 tests from these people, we can start to see a clear(er) picture of what is going on and how reliable or not the TTV is or is not.
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Unread 11-21-2005, 05:57 PM   #194
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Quote:
Originally Posted by Cathar
Was referring to data that you know that I don't have the permission to publish......
Said data projected a unit thermal resistance lower than that of the inherent thermal spreading resistance of the copper in the unit.

Just wanted to make that point clear before leaving this.

Cathar, not according to my analysis.
When R=C/W
where W=total heat dissipation through all of IHS
C= Local IHS Temp-Coolant Temp
which is the definition used for TTV testing in July 2005 pdf
W distribution will depend on heater/heat-die dimensions and thermal characteristics and to a,probably, lesser extent the cooling properties of wb.
The case Post133 illustrated was a uniform flux 1x1cm die with 0.33x0.33mm Local area Temp(width of groove 0.33mm)
For 270,000w/m^2c on 14.4x14.4x1mm case
A tapered Flux Channel 14.4x14.4mm >0.33x0.33mm
Cu Resistance=Total Resistance- 1/h(eff)A =3.57949 -0.017861=3.561628775 c/w (Waterloo
This resistance with reference to a 0.33x0.33mm area
Translated to 1sq cm ref area this is 0.003879 c/w
This a major part,but not all, of the total Resistivity of 0.003898c/w/cm^2

Edit Corrected pdf date to 2005

Last edited by Les; 11-21-2005 at 06:07 PM.
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Unread 11-21-2005, 05:58 PM   #195
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Quote:
Originally Posted by Orkan
At the end of the day... I doubt switching from apogee to storm, or storm to apogee would grant one a higher overclock.
hmm - is that not the implication of the hypothesis that the lower IHS temperature results (partly?) from a different block geometry leading to poorer IHS to Die contact?

(assuming it is the efficiency of cooling the die as a whole that determines the o/clock... rather than better cooling of hotspots etc.)

if you look at the "actual CPU testing" figures swiftech link to just before the graphs on the apogee page (which are for a dual a64) then the storm figures give an IHS temp that is (slightly) lower than the CPU probe in each case, and for the apogee the same or (slightly) higher than the CPU probe. that seems to suggest that there is certainly a possibility that the accuracy of an IHS temperature as a proxy for die temperature may vary between block designs....
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Unread 11-21-2005, 06:10 PM   #196
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Les, I was not referring to the Apogee data when talking about defying physical possibilities. That comment was referring to data of a tested waterblock that I cannot disclose or reveal the original data.
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Unread 11-21-2005, 06:14 PM   #197
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Quote:
Originally Posted by Cathar
Les, I was not referring to the Apogee data.
Fully aware
I have no problem interpreting the " data that you know that I don't have the permission to publish" in the same manner.
Suggest you review your analysis
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Unread 11-21-2005, 06:22 PM   #198
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We shall see.
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Unread 11-21-2005, 08:14 PM   #199
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*continues eating pop corn while reading the must intellectually demanding thermal testing soap opera ever*
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Unread 11-21-2005, 08:26 PM   #200
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lmfao

hey man... pass the butter/salt
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