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Testing and Benchmarking Discuss, design, and debate ways to evaluate the performace of he goods out there.

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Unread 09-04-2003, 10:21 AM   #1
RoboTech
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Default Standard die size (surface area)

As I'm sure most of you know, C/W values are proportional to the die contact area. Since I am considering re-making my die I am once again re-thinking the surface area to use. My first brass die is 84 mm2 (XP T-bred) but given the chance to do it over...

I suggest we "standardize" on 100 mm2 die surface area. This is a nice even number that also matches the Barton core (101 mm2). The Opteron and P4 with integral heatspreaders are too big for a die sim IMHO.

The aspect ratio of the die (width x length) is probably much less critical than the total surface area. The Barton core is 7.42 x 13.61 mm. I'm thinking of using 7.50 x 13.40 mm for my new Cu core => 100.5 mm2 or maybe we should just go with 10 x 10 and not worry about it.

What do you think... ?
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Unread 09-04-2003, 11:05 AM   #2
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Maybe 10 by 10 would do.

The P4, as we all know, has an IHS (Integrated Heat Spreader), but without it, the die is the same as on an Athlon.

Anyone know the die size of a P4?

The White Water and the Cascade have been designed, to some extend, with an Athlon core in mind. So maybe it doesn't matter, maybe it would have a negligeable effect?

Any thoughts?
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Unread 09-04-2003, 11:22 AM   #3
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I think it should be the exact size of the core, ignoring any IHS. If you want you could take an IHS off of a dead P4 and sandwich it in there for P4 simulation (exact die height would need to be done then also). A design such as the one Cathar made could not be tested correctly if the die size did not simulate the real thing.

What about in a real die, there are hotter spots on the die itself, such as over where the cache is located, how do you simulate that?
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Unread 09-04-2003, 11:28 AM   #4
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If I remember correctly the P4 die is 134mm^2, and expected about 100mm^2 for the 90nm prescott...

and gone fishin- first, the cache is a cool spot, and second- its impossible to simulate the hot spots because we don't know where they are or just how hot they are. To accurately simulate a die that well would probably blow away even BillAs $20k simulator cost

I think 10x10 is pretty good; larger than a t-bred but smaller than a P4, and probably very close to 90nm prescott/athlon64
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Unread 09-04-2003, 12:06 PM   #5
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Gone_Fishin: how do you justify having to use an IHS? I just want more details as to what you're thinking.

Otherwise, The White Water and the Cascade may suffer a marginal performance hit (or boost?), from a 10 by 10 mm die, but is it significant?

The various hot points of a CPU core really can't be simulated, because there's no data available on that. I believe that it's sufficient to simply state that the heat die must generate "X" Watts. I don't believe that any waterblock is intentionally designed to take advantage of the distribution of the heat load, within the die.
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Unread 09-04-2003, 01:28 PM   #6
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Quote:
Originally posted by bigben2k
Gone_Fishin: how do you justify having to use an IHS? I just want more details as to what you're thinking.

Otherwise, The White Water and the Cascade may suffer a marginal performance hit (or boost?), from a 10 by 10 mm die, but is it significant?

The various hot points of a CPU core really can't be simulated, because there's no data available on that. I believe that it's sufficient to simply state that the heat die must generate "X" Watts. I don't believe that any waterblock is intentionally designed to take advantage of the distribution of the heat load, within the die.
Well, if your goal is to simulate a given core and how a waterblock reacts with it, the P4 has the IHS with its extra tim so why not use one. Not too many people are removing the IHS and running any waterblocks on the die itself (there are a few exceptions I've seen). Now that just doubled the workload for an all in one tester hehe, test with bare die to simulate older AMD, then test with IHS for P4 and future AMD cores and make a new die for that too while you're at it. Who in their right mind is going to take on such a task? So I guess in steps your alliance and says it's alright to cut corners, just not too many of them?

From what I've seen you discuss so far I get the impression that you will certify (and I use that term loosely) using a low resolution, shaky accuracy, not so steady state water temps, and now a die size that does not match any processor.
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Unread 09-04-2003, 03:17 PM   #7
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You didn't answer my question.

Let me put it another way: what is it about the IHS that makes it so different, that we'd have to resize the die?

Obviously, as the name implies, it spreads heat. However, it's really thin, so the heat isn't going to spread very far at all. What we know for sure, is that the IHS can have a gradient of up to 3 deg C. So the IHS spreads heat, so that the cooling solution (water block, HSF) can handle the heatload a little easier, but at the cost of a gradient.

I have to assume that Intel didn't do something stupid here. Obviously the IHS also protects the core from being crushed, so the gradient is a sacrifice?

If you want to know the actual temp that you can expect from running a tested block, on a P4, then it's an added difficulty, but isn't that the case regardless?



As for the water temp measurement, that's a discussion in progress. If you want to infer that standards have been established, then I can tell you that you're wrong.
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Unread 09-04-2003, 03:58 PM   #8
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Quote:
Originally posted by bigben2k
You didn't answer my question.

Let me put it another way: what is it about the IHS that makes it so different, that we'd have to resize the die?

Obviously, as the name implies, it spreads heat. However, it's really thin, so the heat isn't going to spread very far at all. What we know for sure, is that the IHS can have a gradient of up to 3 deg C. So the IHS spreads heat, so that the cooling solution (water block, HSF) can handle the heatload a little easier, but at the cost of a gradient.

I have to assume that Intel didn't do something stupid here. Obviously the IHS also protects the core from being crushed, so the gradient is a sacrifice?

If you want to know the actual temp that you can expect from running a tested block, on a P4, then it's an added difficulty, but isn't that the case regardless?



As for the water temp measurement, that's a discussion in progress. If you want to infer that standards have been established, then I can tell you that you're wrong.
I clearly stated in my post why I would justify using the heatspreader. Anyone should be able to distinguish that I suggested to make a new test die when the core size of real processors change, like with the new AMD's coming.

I in no way said or implied to resize the die to the size of the IHS, I said add the IHS on top of the test die (just like the real mcCoy). And I know you know I know what a heatspreader does.
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Unread 09-04-2003, 04:05 PM   #9
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My theory for the heatspreader is since its made from copper, it will spread heat better for cheap stock aluminum heatsinks.

I also don't think it should be used for testing. Having to test the waterblock twice as much for an extra mounting interface to add error to the tests seems ridiculous to me; while it will change waterblock performance, it will not change the relative performance.
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Unread 09-04-2003, 04:39 PM   #10
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I agree with an 100mm2 die, as every new chip model and generation is going to have a different size and shape, so matching a specific one that's going to be obsolete over time dont seems good.

About square or rectangular, It's more a matter of taste, I like it rectangular, as in some disigns can be tested the impact of orientation. To keep simple numbers, I like 8 x 12.5 as it matches the 100mm2 goal.
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Unread 09-04-2003, 06:13 PM   #11
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Quote:
Originally posted by Zhentar
My theory for the heatspreader is since its made from copper, it will spread heat better for cheap stock aluminum heatsinks.

I also don't think it should be used for testing. Having to test the waterblock twice as much for an extra mounting interface to add error to the tests seems ridiculous to me; while it will change waterblock performance, it will not change the relative performance.
quote, "while it will change waterblock performance, it will not change the relative performance. "

??? WTF does that mean?

Picking a die size out of thin air because it is conveniant as opposed to copying a real die size seems foolish. I guess everyone has a different idea of what "simulate" means. For some it is close enough, for others it means to come as close to the real thing as possible. If our combat fighters went into flight simulators fighting the red baron, we'd be in trouble.
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Unread 09-04-2003, 06:23 PM   #12
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In general I have to agree a standard 100mm2 regradless of shape is the best. It's the acceptable average. It will give accurate results over the widest array of samples.

The only time there would be a wide discrepency is for highly customized blocks that are designed to concentrate the cooling directly over a specific sized die.
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Unread 09-04-2003, 06:26 PM   #13
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Quote:
Originally posted by sevisehda
In general I have to agree a standard 100mm2 regradless of shape is the best. It's the acceptable average. It will give accurate results over the widest array of samples.

The only time there would be a wide discrepency is for highly customized blocks that are designed to concentrate the cooling directly over a specific sized die.
Aren't those the best kind? Why waste time and money testing lower performing designs of yesterday?
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Unread 09-04-2003, 07:19 PM   #14
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Quote:
Originally posted by gone_fishin

??? WTF does that mean?
it means it will take your measurement from say .23 C/W to .25 C/W, so you will end up with a different number. But it will affect all waterblocks linearly- if you ranked the waterblocks tested with and without the spreader you'd get exactly the same order.

The problem is, pick a P4 die size and shape, and it hurts AMD optimized blocks; the opposite is also true.
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Unread 09-04-2003, 07:37 PM   #15
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I think that we should discuss this some more.

Gone Fishin: while I agree that it may make a difference, what I'm looking from you, is your pespective, the technical details of why an IHS should be used. Wether or not I know where you're coming from, is irrelevant.

Can you share your insight on the issue?


Zhentar: are those numbers (0.23 and 0.25) real or just an example?

No tester really, really wants to run a second batch, with another heater, with or without an IHS. It can involve, among other things, building another heater, applying a TIM as Intel does to the IHS, which we're not really in a position to reproduce (pending a source of the TIM material that Intel uses).

But we still have to have some kind of justification as to why we wouldn't do it, if we decide not to do it. We should also try to quantify the error, if any, that this decision is going to have.

The purpose of a test bench is to measure the performance, by reproducing, as possible, what a typical PC might put the block through.

One might even wonder if the block should be mounted sideways, versus "flat down".
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Unread 09-04-2003, 07:57 PM   #16
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pulled those numbers out of my ass.

But for the reason why not to do it; it introduces error; accurately reproducing a TIM repeatedly is very difficult.

Going off of the 8C gradient for an 80 watt heat source we've seen and debated, the TIM between die and waterblock has .1 C/W heat resistance, the die/IHS will probably be similar, and this will be uniform for all blocks mounted on a P4; therefore the effect of any IHS waterblock tests would only be to find this value; and totally useless at that being an inaccurate simulation of what we are measuring.

Mounting sideways vs. Flat down will simply stress the mounting and the TIM; it would increase error of the system without aaffecting block performance; the sideways set up tests the quality of the waterblocks mounting, and as this will be the most difficult part to keep uniform and accurate, should not be stressed to keep error between mountings to a minimum.
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Unread 09-08-2003, 05:31 PM   #17
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Isn’t AMD going to be using I.H.S in their CPU’S? Isn’t the point of this simulator to simulate constant heat being emitted by a complete CPU? If it happens that the CPU has a I.H.S then the Die simulator should simulate a CPU with an I.H.S.
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Unread 09-13-2003, 10:09 PM   #18
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To make the square die can take to concentration of heat in the corners. That is something that I don't believe it happens in the core. I think that a circle of 100mm.2 is more representative of the heat of the core, since the concentration in the superior edge would be almost same and there would not be concentration in the corners. I am to build one and a lot I would like to be able to arrive to a definition with regard to the dimensions. Pardon for my horrible English.
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Unread 12-06-2003, 01:29 PM   #19
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Let's stir this up again!


The P4 die size is 146 mm2, AMDs Opteron is 164 mm2, and Athlon FX at 193 mm2 (none of these are confirmed!).


I'm against the round shape, but I do see the logic behind the suggestion: it minimizes the area of secondary loss.


There's the possibility now, that 10 mm by 10 mm may be either out-of-date, or for future CPUs only, but nothing that is "current".

So...

10x10 (100 mm2), 12x13 (156 mm2), or 14x14 (196 mm2), or any other suggestions?


Personally, I will run tests with a 10 by 10 die, but strictly for the purpose of obtaining results with a higher heat flux. 12 by 13 is looking mighty good right now.
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Unread 12-06-2003, 02:06 PM   #20
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goes up to 18x18mm @250W (that I actually know of)

take your pick, matters little through the sizes you listed,
and makes the results no 'better'
do you know what die size JoeC is using ? (its been posted)
the existence of Intel TTVs is a matter of public record, do you think in only one size ?

understand Ben that you cannot define any standard
for the die sizes are changing all the time, a die shrink on every road map that I know of;
and until you can demonstrate relevance, its all hot air

plenty of thermal images of CPUs around, never seen a circular one
- I would enjoy seeing you demonstrate its superiority, or even relevance for that matter

until you are able to test, all you can do is speculate - and post;
or, perish the thought, look at the testing of others
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Unread 12-07-2003, 01:10 PM   #21
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Intel TTV?

Oh do tell us more (or should I just Google for it?).
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Unread 12-11-2003, 02:08 PM   #22
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Hum... had to e-mail Intel about that one!

Xeon TTV specs seem to point to a 0.448 by 0.363" die (11.4 by 9.2 mm).
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Unread 12-19-2003, 09:19 AM   #23
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Ben

http://www.vr-zone.com/?i=308&s=1

and your next analysis/prediction about die size is ?
(when will you learn to not speak about that of which you are uninformed ?)
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Unread 12-19-2003, 03:21 PM   #24
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Well, I'm certainly not going to bring up Intel's dual core CPUs, coming in 2005 and beyond...

...but instead of ranting, why don't you forward a hint at a solution? Yours is getting tiring too.

Intel specs seems to mention something about a "correction factor" to the TTV: do you know anything about it?

In the mean time, I'm in contact with Intel, about the TTV. Now to see if I can get something useful out of them...
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Unread 12-19-2003, 03:37 PM   #25
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Ben

I posted a link to a 'public' website
Swiftech has NDAs with numerous companies, I am precluded from being useful

you will not find one size to fit all
nor will you find that anything is constant
other than the all too apparent increase in watt density

does 2005 seem so far away to you ?
not to me, planning and product design is done in advance
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