Re: Apogee from Swiftech...
would observe that, again, we encounter a "case" temp;
and no die temp jd this discussion has nothing to do with DIY testing, more about getting it right different activities for different purposes and I agree with you, getting way to complex to justify what is barely the beginning of a huge - unfunded - R&D exercise to what ? test a wb ? a misplaced allocation of resources better spent on something that cools what is the most SIMPLE setup that can be made to yield that info necessary to define something useful that can be compared ? |
Re: Apogee from Swiftech...
Sadly... A PC with a custom PSU feed direct to CPU voltage regulators, and an aircon'd room. *runs*
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Re: Apogee from Swiftech...
whats to run from ?, this is the same old dilemma
this heat die thing is outta hand, the more we learn the more we want what is missing is a cost/benefit analysis |
Re: Apogee from Swiftech...
break it down then.... spec up the current "ideal" testbed and price it... problem comes with quantifying benefits. cost/benefit of heatdie vs ?
A suitable alternative has to be found before benefits can be established... or are we taking a PC as ? |
Re: Apogee from Swiftech...
my problem here is that I'm pigsh*t ignorant about CPU testing, for example what are real IHS temps on a CPU ?
and if TTV temps are not valid, how are CPU case temps different ? does each die size require a unique test ? (because we cannot figure out the scaling rules ?) but I don't like where the heat die is heading; too many 'requirements' with too little understanding of the mechanicals -> who is going to make one and test and debug the design, then build a 'good' one ? not me ! we need to match our expectations with our budget, both talent AND $ |
Re: Apogee from Swiftech...
I miss the days of good ol' CPU based testing. Man things were simple. This is still the way nearly every HSF unit is tested. You clamp one on, test it. Clean off the CPU... clamp second one on, test it. ... viola
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Re: Apogee from Swiftech...
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Would have to choose a mobo, choose a bios rev, choose a cpu generation and speed. Stick with it for all testing. One rig for Intel, another for AMD. All testers conform. Problem will always be defining the wattage that the CPU is producing at any given moment. Time for electronics engineers to step in... find appropriate measuring points to establish incoming voltage and ampage. Find someway to provide that power smoothly rather than the ripply voltage-regs of the PC and it's PSU.... You have a PC (you're sat at one I assume)... grab a probe and measure... no-one goes to lengths shown in AMD TechDoc I linked to above to measure realworld (worthy of a read if you haven't already - s'how AMD recommends one does it for a heatsink)... everyone just whacks it on the side of the IHS or uses ondie as reported by bios / windows software. |
Re: Apogee from Swiftech...
Hi guys
I have a little experience testing with CPUs. I have encountered some problems I am not certain are surmountable doing my old "solder in wires trick" with AMD64s. So I am laughing a little at the idea of Bill heading towards CPU based testing while I think on using a die sim instead. I would chime in that I think a die temp and an IHS temp should both be taken if you're using a CPU. Otherwise you'll never know if the internal TIM joint is being degraded. That leaves only AMD systems, but they are the ones with IHS TIM problems in the first place! I assume what Bill is planning is ONLY taking the IHS temp and then relying on a correlation back to die temp provided by Intel. Sounds ok to me, but not sure it's going to properly address the whole real picture (look at Groth's picture again). I could do these sort of correlations for AMD with my current testbed, but I really feel like within a few weeks of testing the processor is going to break. |
Re: Apogee from Swiftech...
you should laugh, I'm too frustrated
I do not believe that a technically 'correct' heat die soln is economically within our grasp I accept we want it, who will fund it ? making a die as we are discussing is a long project with little expectation of success as the requirements cannot be defined (at least by this group) no pH, no Intel info not public - which means nothing on present or future TTVs; I do not have a TTV whatever is used as the source, it must be durable else all must be correlated over and over (jeez, back here again) |
Re: Apogee from Swiftech...
OK I am talking in Pro/Chat with Scott.
I think I might have what is the best solution for me: 1) Test a waterblock with IHS 2) Pop off IHS and retest 3) Fiddle with the CPU until I hit upon a method to reliably reaffix the IHS in a way that yields similar temps to (1) but the IHS separates from the CPU when I change coolers so I don't destroy my CPU. There are a lot of advantages to this: I could put a TC into the IHS and then get tim joint estimates I get better CPU diode temps than you can from any motherboard I don't destroy my CPU within a week or so I don't have to argue with the die sim folks I get the flexibility of choosing whether to test bare core or IHS Is there a disadvantage? It might take some fiddling to get the IHS back on totally reproducibly It is an alteration from a pristine CPU (but so was this right?) |
Re: Apogee from Swiftech...
"It might take some fiddling to get the IHS back on totally reproducibly"
beginning and end right there indeed; not just 'as good', but also not 'too good' EDIT pH; if this were one of your professional experiments, what would you require to qualify that assy ? Talcum ? |
Re: Apogee from Swiftech...
pH
think simple, you only have to characterize the TIM joint once then assume all good joints will measure the same ck and test, no removal your measurement depends on the groove and TC attachment method, need to be really well defined and executed |
Re: Apogee from Swiftech...
From an experimental standpoint, the durability issue of the CPU+IHS is too huge to get around. That is why I'm focusing on it first. If the CPU is ripping out of the socket and breaking then I'd have to constantly recalibrate/replace CPUs. That's a dealbreaker. My thought is that if you have the tc in the IHS that you can then just check the quality of the IHS/CPU joint and shoot for a constant dT there. If you have it then your mounting force/mounting geometry is "ok" and you can go forward with the test. A simple crosscheck, or no?
The other huge problem with using a CPU in a lab would be the power estimation. I have no good homebrew solution for that one other than insulation and calculation based on dT of water across the wb plus flow rate. |
Re: Apogee from Swiftech...
So am I the only one who thinks of Commander Keen every time I see the work Apogee ?
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Re: Apogee from Swiftech...
Oh and on topic, the plan pH just posted up there about the removable IHS is interesting but I instantly thought of the same thing bill replied with - how do you make sure you are not getting it too good, so its unrealisticly good compared to a stock IHS.
But then it hit me (because I am slower than your average geek I think) that accuracy compared to a pristine CPU is not that important as long as you are very close. (so that data from one test rig can in some ways near the data from another test rig with similar back end equipment, and using a pristine CPU) But keeping testing accuracy across a test set is something I would be concerned about. You would need to be able to show that with the same block, same coolant temps, etc... that the only variable that changes in a dozen or so mounts is the IHS and the block being removed and remounted. And that after that the temps are very consistent across all the remounts... if you see to high of a variance then you know its not a viable solution. Thats just my take... now back tomaking smart ass remarks... |
Re: Apogee from Swiftech...
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Yeah my impression in this was that accuracy of the temp and flow measurements are extremely important and any errors lead to errors in calculating the wattage from the CPU. Also the dT from waterblock inlet/outlet is often very small, no? How about calorimeter type setup with the cpu under load (similar to what one would do to measure a pump's heat input to an insulated loop). Just let the system water keep increasing and insulate the whole thing (better if no pump is involved, just a tank of insulated, well-stirred water) but anyway, is that even remotely feasible? The only issue with that which I can see (besides the actual mechanical test setup) is that the cpu will dump less heat into the system as the system temp increases, and more into the motherboard itself. However this might be a small amount (neglible) or might not be, but won't know till check it, right? Has anyone characterized these losses before? |
Re: Apogee from Swiftech...
The interesting part of pH's idea is that if say 2-3 blocks were tested with and without the IHS, we can get an idea of what role the IHS actually has in terms of core temp. My thought is that the IHS will make the die temp go UP in a linear fashion regardless of the block when measuring CORE temps. I could be wrong but I don't think so. So, Block A reads 15C with IHS and reads 12C without IHS. Block B reads 14C with IHS and 11C without IHS. Block C reads 13C with IHS and 10C without. At least, I hope that is the case, in which case, couldn't the IHS be taken out altogether to remove that variable?
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Re: Apogee from Swiftech...
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The load (60 - 90 lbs) will be split between the rim of the IHS, and the actual core. In what proportion, we do not know. What we do know is the load for a bare die, from old specs. I see this headed one way (for those that use a test die): 1-use a real IHS (since it's durable) 2-mount it as a free floating item on top of a heater die (alignment?) 3-do a temp measurement, Intel style (groove in the IHS) 4-clamp to old mounting specs (25 - 30 lbs) PH already does remounts for one TIM variation; now it's remounts for two TIM variations. Simple. JD; Intel or AMd, makes no difference. What it comes down to, is what offset you're going to apply to your results (raw data), to figure out what a user would get. |
Re: Apogee from Swiftech...
Scott
the IHS and TIM joint(s) may be modeled effectively with resistors Ben compare (speculate on) the repeatability of the assembled TIM joint vs. a factory one ? (Shin Etsu is silk-screened, that grease will not be used; solders are out, no procedure; we know AS is not used; next ?) |
Re: Apogee from Swiftech...
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But what if the IHS spreads the heat out over a larger area? Then removing the IHS would in no way reflect real world situations, as we've established that most keep their IHS on. |
Re: Apogee from Swiftech...
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I'm not sure I agree, in the strictest of senses. How many waterblocks would you have to test before you felt confident saying there is a linear offset, so then no need to test with an IHS - 3? 4? 5? It would only take ONE block not in agreement to disrupt this 'conclusion.' |
Re: Apogee from Swiftech...
Absolutely right Al, but if 3 were in agreement, I think we would be good.
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Re: Apogee from Swiftech...
Eh or a nonlinear relationship (then you'd need LOTS of points right?)
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Re: Apogee from Swiftech...
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Re: Apogee from Swiftech...
I would think that as long as you're measuring it with a tc then you gain a bit of confidence in the whole system. The "do it once and forget it" troubles me, and the "skip IHS and assume it's just an offset for all blocks" also troubles me.
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Re: Apogee from Swiftech...
OK since think simple is one piece of advice...
What about just trying to work a piece of fishing line in between the block base and the IHS top when remounting and break the seal by "flossing" the CPU? Simple enough? |
Re: Apogee from Swiftech...
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A more rigid waterblock base would put more pressure direclty on the core, and result in a lower dT (core to IHS temp). This is one reason I highly doubt a constant linear offset would work. Quote:
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Re: Apogee from Swiftech...
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Re: Apogee from Swiftech...
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I'm not counting on the ability to replicate the inside TIM joint, exactly the same way that it is manufactured. I'm counting on the ability to apply an offset, which means that we have to have a repeatable TIM joint during testing, both inner and outer. So... this means that we have to have a TIM joint that can consistently be repeated. (great, now that I'm caught up...) How do we make sure it's repeated? Back to Cathar's objection; it's not quantified. PH remounts 5 times, and measures variations, but it doesn't actually quantify the TIM joint. Quantifying it would require a temp measurement on both sides of the TIM joint. So... we add a thermal probe down low in the heat die (horizontally, of course), and do a dT between it and the IHS?!? (how much more coffee am I going to need today to sort this out?:confused: ) Orkan; I don't think that anyone is going to dispute that an IHS does spread out the heat. What's really at issue is how significant it is. Then it comes down to wether or not it can be compensated by an offset, when using a straight die. (Darn, ya'll have caught up to all this while I was typing!) Someone (Les? Groth?) projected a 1mm thick IHS, but it looks like it's actually 1.4 mm. Flossing ?!?:confused: |
Re: Apogee from Swiftech...
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How significant the spreading is will depend on the specific waterblock cooling properties, I suspect. However the variance may be negligible, again, won't know till we try to quantify it. Also confused on the flossing, PH - are you talking about between the actual core and the IHS or just around the edges/seal of the IHS? |
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