no, its the pins (the dP indiicates)
need a good pic of the pins

OK, (same comment) just think higher density (12 rows x 17 columns) in a 1.33" sq array... :)

Edit: I'll try to post some pics later tonight or tomorrow.

well come on, cough up the pic

...not even the NexXxoS XP data on the same testbed? With the block assembled incorrectly, 2/3's of the flow occurring directly between the inlet and outlet between the top/middle plates, only 1/3rd of the flow making it into the jetted/pinned area, the base-plate flexing under even slight pressure, and having all that produce h(eff) results that would put Les's and my theory out by a factor of 10?

product descriptions Cathar
published data in the public domain

you and I discussed this data, and its problems
this is not the place to bring up such, nor do I still have access to the data

Ta
Was modeling on 12x17 in 40 sq mm not 34sq mm - difference significant.
More dimensions appreciated

I can't help but feel some of Roscal's comments were directed my way. Even if they weren't, I feel that I should explain my motivations.

As always, I view my goals as that of obtaining the highest possible cooling performance from a waterblock design. That is pretty much all that concerns me, and pursuit of the Storm/G7 with a "hang the cost" approach is pretty much evidence of that.

Where I get concerned with all of this, is that I just want to see waterblock design pushed forwards, not backwards. The Apogee is a well thought out design with a lot of merits, of that there is no doubt. It suits Swiftech's marketing goals to a tee, and that's always a good thing for Swiftech.

I guess that my main concern is that one design is not being passed over or shelved on the merits of test data from an individual testbed in which the heat die temperature is not known, the variations in effects between heat-die and IHS TIM layer interaction is not known, and the size of the heat die is not known. To put in so much effort, and to have one's work effectively dismissed or sold short based on the results from a testbed where so little is known about what is actually happening at the CPU/heater-die level, just makes me feel no small amount of chagrin. If I felt that there were no doubts, then I would be a lot happier to suck it up, roll my sleeves up, and try harder.

I guess I could some it all up as feeling like the designer of Betamax in a VHS world.

I think these results are due to the TTV used for testing. Unknown is the size of the heat element or the temperature of the element. We have no idea the TIM relationship between the IHS and the element etc, etc. How can this be a useful tool? Isn't the TTV (from what I've read on it) used for HSF validation only to then be revalidated elsewhere, as in, don't rely only on the TTV as your only means. Again, using an AMD chip and measuring the IHS temp means nothing to me. We used to make FUN of people that performed this type of testing eh? Now we are supposed to take it as the word.

Furthermore, you guys remember this article? http://www.bleedinedge.com/reviews/a..._temps_01.html IMO there is little difference between the TTV results and the results obtained in this article, both fairly useless. Same concept at work here, no different. I do recall all of us making lots of fun at the above article. What gives?

then it is agreed that there is not only one method ?
or just that 'that' method is 'wrong' ?
absolute or relative ?
if absolute then the limits must be defined, which they are - which these apps have nothing to do with
- so we are left with a heat source having certain characteristics
what is the big deal ?

ah yes Scott, "take it as the word", what a burden are facts in conflict with opinion
are the conditions not stated ? then that is the word to be listened to, and to use to 'adjust' the data as appropriate

that article is a bonehead comparison, pay attention to definitions (case temp is defined as the IHS temp measured a very specific way)

are the TCs reading the same temp ? same place ?
what is your point/question ?
what are you comparing it - or any heat source - to ?
or are you questioning sensor placement ?

data is no more than data; if reproducible it is good, if intelligible it may be useful

Not at all, it's for people who think that Storm can't be beaten because it comes from you. I see a lot of stupid comments on forums about that story Apogee Vs Storm, I am under the impression that we've got kids in a fight to know who got the best toy and Swiftech brake their dreams with its new model... "OMG, Apogee is 0.5°C better @100W, what a drama", it's the feeling that a lot of people give me, but they aren't be able to understand what tests give us and what they represent really on a real machine. There are so many factors involved in these measurements that you can't say what are exactly the absolute performances, it's always relative to others factors like the heated system in this particular case...

Actual processors have an IHS, we can't neglect it (should we?) and if someone think the contrary, he's wrong. You want correct data? You have to replicate a similar system to reproduce as close as possible the thermal behaviour of a real product, naked dies are good for some things, not for all of them. No difficulties to understand that fact I think ? I don't say that TTV is the St Graal, it's a different way to measure, but why TTV will be less interesting than a simple die? Show us some true evidence if you are so categorical (it's a general question, not yo you Cathar). You're arguing using some pretexts which can be determined and measured if a good cross study is made, but nobody makes it, is it my fault? Effects are common to all WB measured on a same system and this is why multiple mounting are required for example, we don't need to know how TIM will react exactly because it will react in a same manner each time (flat IHS, same pressure, multliple alternate mountings, etc.) and you could control it if you really want. All is relative !! Again, thermal management is not a simple science, not at all, especially int this case...

Bill, the big pink elephant here is what is the DIE or heating element temp? No one knows. The surface of the IHS temp is useless IMO without knowing how the heat source is being cooled. You dont have this in die sim testing. That is the big deal.

No wrong. I could give a rats ass if the apogee is a better block. The one and only issue I have here is the test method and the device being used (TTV). One must know die temp not IHS temp. Yes the IHS plays a factor on all current cpu's but so what? Is it impossible for the surface of the IHS to be shown cooler with one block yet the the actual heat element underneath hotter than the other block?

There are two threads here and here which are attempting to meet these issues head on.
Perhaps we would benefit if you expressed your validity concerns there.
You are waffling

it doesn't really matter, cancels out with the same source - or a correlation is developed if the interest and data are sufficient

the Swiftech wb data sets utilize the same source,
both the 6000 and Storm have been tested by others,
and . . . .

I still do not understand the technical issue
as with all things, many ways to skin a cat
applies to product design as well as testing

I really dislike the idea of using a IHS CPU for testing. The IHS has a TIM layer that meets the die of the CPU no? How many times can you mount a block to it until that TIM layer starts to degrade? How many times do you use the same TIM joint from the heat sink/water block to the CPU? I only use it once. Hell sometimes not at all if I feel I screwed up the mount. How many times does AMD or Intel think their CPU will be remounted? I doubt they figure multiple remounts into their engineering of the IHS and TIM layer seeing how 99.9% of CPU's only get mounted once in their life time.

Also the IHS helps spread the heat more evenly eh? So how is that different than a die sim which the heat is spread pretty evenly? Only difference is TIM layer and the thickness of the IHS itself. I don't see why that would change things so dramatically.

I hope to mill a new die sim or 2 during Thanksgiving if I have time. Should I mill a IHS to mount on top of the die aswell?

Well, not really. If the heat-die to IHS TIM interaction is varying with respect to block geometry, which I strongly believe was shown with the XP results, then it does matter.

If the IHS is not being pushed against the heat-due strongly, or there are variations, then the thermal probe will read differently when the IHS is making poor contact with the heat-die. If such is not quantified, or that variable not removed, then what is being measured?

In order to remove this variable, the simulated die and the IHS need to be a single-piece affair, and in doing so the issue is solved. When can then use TIM layer extrapolations/experiments/calculations to apply a project temperature delta when a die->IHS TIM layer is present. Doing so does not take into account the full variability of this thermal interface, but attempt to derive a "clear picture" of waterblock performance when such a variable is in effect seems flawed. No?

no Scott, you do not want the die temp to characterize the device thermal resistance
what you want is the 'sink-to-air' dT (or wb bp-to-coolant)
no matter what, you will have a TIM joint; Intel grooves the IHS and includes the joint, AMD grooves the sink excluding it - net effect is the same after calculation
both methods are imperfect, but understood

the die temp is a fiction

nikhsub1> TTV TC is just above the core center, thermal gradient is only one way because power comes from die (hottest part), if IHS center is cooler then core is cooler and vice versa, the opposite isn't possible, it's not physical. If really you are motivated, nobody prevents you to control multiple points (die T° in addition to IHS center for example) if you really want to see how linear or how non linear relations are, choose a method and have more data. Die temp isn't the only interesting point.

jaydee> IHS is bigger than a die, it's not the same thing to put ~1.4mm more height (IHS thickness) on a 10x10mm die, than put a 30x30mm IHS on a 10x10mm die. And it's not the same to make a 30x30mm die (Joe on o/c.com makes one, no? It's meaningless), it's absolutly not equal to a die covered by a 30x30 IHS part !

For the TIM between die and IHS, you can solder it if you want or use epoxy, no matter and it don't change for tests. Intel uses epoxy to this place, it's not liquid thermal paste (pump-out effect is always possible)

Epoxy will still be subject to pressure based variations. Solder less so.

Cathar
you are postulating an 'event' to account for extraneous data
i.e. the 'durability' of the IHS TIM joint
I do not question its finite # of cycles, but this has no bearing on the new heat source

you question the flatness of the heat source IHS when such is presumed to conform to the sink, clearly when the relative stiffness of the 2 are reversed deformation of the bp will occur
- but its best characterization will still be on an IHS

the 'problem' with these heat sources is that they cannot be referred to, and they change -> which mandates a new data set

Pressure is a known value if you do well the tests and multiple mounting are always here to ensure consistency, no matter than TIM is changing. TIM doesn't change radically in 2 days to give a 3°C gap, this is a false pretext. Perhap's change will be visible in 2 years because you are doing only 1 or 2 tests a month and what will be the variation at these 2 different moments? 0.01°C? 0.1°C? 1°C? more? Nobody has the answer because nobody made measurement (don't think Bill made such test?) and it's always a special case anyway, no global statement. But to ensure no matter, you make a flash solder on a ultra thin thickness between IHS and die and no problem anymore.

IMO, it's the responsability of the tester to program a maintenance period of his die : you fully test a WB and one year later, you test it again and compare, how results will be? How much variations I get? Is die worn? Is TIM changed? etc. etc. A lot of interesting stuff here.

Actually Bill, it was Jaydee that postulated the durability.

I am questioning the effects of block geometry, and the applied pressure and deviations in effect as a result of this. 1.5mm thick copper flexes fairly easily, we know this. The edges of the IHS are mounted against the packaging substrate with a compressible bond. The IHS will warp and flex in accordance with the pressures, and locations of the pressure applied as a function of the block geometry.

You talk about deformation of the IHS and the bp, and I agree, and that is precisely the issue here. If the IHS is deformed in a convex fashion (with respect to the heat die) then the center of the IHS, where the heat probe is, is measuring a point on the IHS that is pushed hard against the block and not against the heat die, instead the edges of the heat die serving as the major point of heat transfer. If a block is convex (or at least less concave) when under mounting pressures, the reverse would be true.

Given such variations, I must express a great deal of frustation about this line of reasoning. The CPU die is NOT the IHS.

I am particularly perplexed by this comment from you:

Sorry? Just what is it that we're trying to cool here?

Dunno about anyone else, but i couldnt give a flying **** at a rolling donut what the IHS temperature is...

The final goal of a watercooling system is to make the die as cool as possible for overclocking. Otherwise, its just for silence (in which case, who cares what the temperature is, so long as its stable - and the waterblock does not effect the noiselevel significantly.

Why do we ignore the die temp? jesus, this seems like backpedalling to make a product seem 'better' than it is... independant tests will show this either way, i guess? Change the test bed so you like what you see? Think i might move house and avoid gravity, i always wanted to use my ceiling!

Isnt 'lowest possible die temperature wrt waterblock design' what we're all after?
I mean, i personally dont care - and wouldnt pay good money for an extra 0.5 degrees, because realistically at the end of the day, it doesnt matter, and its probably not going to effect your overclock a noticable amount... but surely being true to the science of it is actually worth doing?

In my (very) humble opinion, why not machine a single piece die with an integrated IHS, estimate the TIM joint between the two (ie, solid piece of copper, which is both the die and the IHS) and go from there? It would simulate the actual heat spread, allow the die temp to be tested... i dont see the down side.

Don't you understand that die at a lower T° equal IHS center at a lower T° (assuming their T° are correctly taken) ? It's not necessary to be absolute, relative measurement is also valid. Put 2 TC if you want in die and IHS center and take your data, you'll see well the situation... The 2 T° goes up and down in a same way.

I presume
Temperatures are across interfaces (water/copper/TIM/ugh probe)
Flux measured by coolant temp rise
Die temp irrelevant

ok, assuming they are the 'same'

why measure the IHS temp at all, then? Surely the way to test is to make the the die as close to a real cpu as possible.

Why does this remind me of all the reviews you see of a TC thermal-taped to an IHS side...

I give up.

If the simple concept that die->IHS variability cannot be understood, then I really wonder what motivations are really at play here.

Logic seems to have left the playing field.

I'm out. Too frustrating.

I am confused by this. Are you assuming the entire IHS is actually heated evenly?

I hope not.

Ah its debates like this which is why i joined procooling none of this geforce penis extender stuff.

On the IHS i personally prefer to have it added as it simulates the real world but adding with the full knowledge that thermodynamically it makes the results poo as stew points out. The IHS has a number of effects that cannot easily be taken away. If your running a proper testing rig you should probably develop a correction factor / formula / testing mythology to account for said effects but I’ve not seen anyone postulate a a good one or account for it in testing data properly. Doing a bare die without IHS correction is in my opinion worse than an IHS on a repeatable accurate testing rig (set a die up and keep using and make sure that it doesn’t change much). Give me a repeatable real world test over fancy Dan stuff any day.

Looking at the geometry of it i can’t get it into my head how it would beat a storm g4 design but I am willing to accept that this is a gut feeling that could well be wrong, At the end of the day manufacturer testing is good but some independent data would be luvly.

My concern with this block is that it will do well on a test rig and be awful in actual long term usage. The base depth concerns me greatly the reason is it is going to flex and going to flex over time possibly gradually separating from the thermal paste. Also the thinness means that heat cannot be spread easily through the block as there is enough transfer thickness to move heat evenly around. This extra thickness will degrade performance as its ultimately insulation but a real processor is not a single temperature field like a die sim(high conductivity base, heat will follow the easiest path) but a more varied distribution where heat needs to be moved around in the block (as silicon is not conductive).