Re: T junction temp
 

If Tj is a "convenient fiction", then if I understand the concerns of both Incoherent and Bobo (which strangely mimic my initial concerns that I raised privately to you some time back), they are stating that Tc is just as much of a "convenient fiction" as it is just as much of a simplistic assumption as Tj would then be.

Can't have it both ways. If it's going to be a simplistic one-value assumption, then Tj is just as invalid as Tc. Can't invalidate the applicability of one without then logically invalidating the applicability of the other.

Re: T junction temp
 

Tc is a measured value
I said "Tc, where measured and how measured, is just exactly that"
is this your sos Stew ? ignoring what is said ?

read the literature, Tj is a whole 'nother kettle of fish
if that difference is not obvious then I begin to understand your handicap
you have measured neither, so speculate 'bout this-n-that

speak for yourself,
let bobo and Inco voice their own opinions
Inco has stated his opinion here on procooling, it is not what you are asserting (provide your source)
bobo states not much, his forte is questions w/o answers (lots of show but little go)
do not use 'popularity' to justify a technical assertion, state your sources

for this thread the second link in the initial post should be considered (the 1st was more of an intro)
google has thousands on the relationship between Tc and Tj

Re: T junction temp
 

not a question of opinion, a factoid

Re: T junction temp
 

a great post with graphic on the censored forum
http://www.xtremesystems.org/forums/...9&postcount=33
illustrating also the imaginary nature of Tj

the resident wizard is in over his ?, not sure of the 'right' word here
even more significantly wrt his intended program, he neglected to establish a baseline
- to observe the degradation of Tim1 with repeated mountings
(can't be flexing the IHS up and down w/o pumping the grease out)

hi ho

775 anyone ?

EDIT
does anyone recall the Intel (ascribed) phrase of years ago: A cascade of gradients
very well illustrated

Re: T junction temp
 

Tjunction clearly means so little, since it is the thermal sensor that drives all Intel CPU thermal control circuitry.

http://www.intel.com/update/departme...ch/it04021.pdf

Re: T junction temp
 

hello ?
I said to read the literature, try it

Tj is at the surface of the silicon
really basic definitions (the junction part refers to the interface between the silicon and the TIM joint)
you are lost

go to the link in the above post and study that graphic
you may even be able to understand what is being discussed
again, just for you
http://www.xtremesystems.org/forums/...9&postcount=33

post over there, you are boring

Re: T junction temp
 

Haven't had time lately to look at it properly yet (estimate it is going to take at least 10 man hours of thinking). My time is at a premium of late.

Been in college all weekend, vibrational analysis of washing project to do. Its be pretty much get up, put clothes on, goto uni, come home goto bed for the past few days. Today came in at 7:50am looking at leaving soon (its 10:30pm), may repeat tomorrow.

My week looks more empty about thursday, so expect something then.

Re: T junction temp
 

did you actually suffer through those threads ??
suggest a clean slate

obviously a LOT of confusion between Tcore (where ?, when ? - diode/which), Tjunction (on surface, in center presumably - msmt method unk), and Tcase (as defined in P4 docs; on step, in center - with TC)

not at all sure its worth 10 hrs unless you're bored to tears
the original pissing contest was about the necessity of KNOWING "the die temp" for sink/wb design
rather moot now as "the die temp" is presumably a core temp (?), in any case not Tj as alleged
(always moot to me)

a more productive endeavor would be considering thermal capacitance and its measurement
(over a 10hr budget, for sure - lol)

Re: T junction temp
 

Some more info on surfaces, as promised:
http://www.predev.com/smg/intro.htm
http://icrank.com/cgi-bin/pageman/pa...finish.htm&t=2
http://www.mfg.mtu.edu/cyberman/

Instruments:
http://www.flexbar.com/surface-roughness.htm

Plenty more hits in Google.

There appears (to me) to be a number of different aspects that this could expand into; I'll try to list:

-IHS flexion
-Core surface finish
-IHS surface finish (on both sides?)
-cooling device surface finish

Of course by "surface finish" I mean flatness as well as polish (aka waviness and roughness, respectively).

Does anyone know the AMD/Intel specs for those (I know that "something" exists)?


This goes round and round; preliminary data from Les/Incoherent suggests a 5 deg C variation across the die of a CPU (Storm block). If so, what does it mean, for us?

Obviously Tjunction has to be measured or extrapolated, and we agree (or disagree) that it's measured in the center of the die, with the assumption that it is representative.

That aside, we do know that the onboard (in-die) diode is not in the center, but we do know that the IHS groove (Intel style) measurement is centered (Intel dubs it "Tcase").

Clearly Tjunction, as currently "measured":ha: by various mobos, is not representative of the die temperature. pHaestus has a nice workaround (questionned on the censored forum, I believe for lack of understanding), but is that Tjunction measurement representative? I believe it is, simply because it is through the heat flux. I do want to ask (for my own curiosity) "Is it centered", and "Does anyone but AMD know?".

If I groove the backside (only) of an IHS, would it be accepted as a measurement of Tjunction?


Rambling style suxorz indeed.

Re: T junction temp
 

back up
Tj is at the silicon/TIM interface
PERIOD, it is a defined term

use something like Tcore for a (undefined in time or space) silicon temp; for what ...... wants to call a "die temp"
-> 'we' never have had, nor will have, a "die temp"
- in spite of my referring to my old copper slug offset riser PRTD msmts as the "die temp"
should be a 'die sim temp' (my error now plagues me)

you are not going to measure Tj, the act of so doing makes it something else
this is the why behind the multi-sensor calorimeter setups (al la Inco), the 'face' temp is extrapolated
can't do that with a thin silicon heat source
there is 'huge' variability in the silicon, less at the face, even less at the IHS (case), and well averaged indeed in the sink bp

let it be Ben
Tcase (per Intel) is quite enough for sink design
(use a multi-source for a multi-core-sink, being done now in 'industry')

Re: T junction temp
 

I'm perfectly happy with Tcase.

"Multi-core" is incomplete; it's either multiple-die-multiple-core or single-die-multiple-core. I am assuming the latter for testing.

Re: T junction temp
 

I need to think about this stuff and relearn Fourier and heat transfer equations that is why it is going to take me 10 hours. On a side(off topic) notes some time or another I need to put something in the wiki so people understand what turbulence is (it is not simple by a long long way) and get off the whole idea of turbulators and stuff. I did see someone using Reynolds number sometime and that made me happy, think the context was wrong and length and velocity scales were not defined but it was nice.

I have skimmed through a few forums and they are slightly helpful as I need practical experience and some more immersion in the subject. Which is why I won’t post anything sciency now.

Variation across the die is something I should derive as it is fairly simple. The main danger is including too many variables so the model is not descriptive. As an example the washing machine model I mentioned earlier. I could have like 60 variables and make a very good mathematical model of how it’s going to behave or put it in FEA. But in reality I barely know 2 good variables so any model that detailed is going to be awful as I need to fit in 58 guesses.

Key point is stick to what we know and try to ignore the rest. To give another engineering quote (this is becoming a habit):

“An engineers dream is drawing a straight line through a complex double log plot”.

And Stew I have believe your point of view more than Bills on this and I find your view far from boring.

Re: T junction temp
 

this thread might be of interest bobo.
http://forums.procooling.com/vbb/showthread.php?t=12899

dunno if you'll get a reply here, everyones thrown their toys.

Re: T junction temp
 

yeah maybe my neutrality wasn't such a good idea. See if anyone posts if i do something good, i do miss those guys.

Re: T junction temp
 

Processor Performance, Packaging and Reliability
Utilizing a Phase Change Metallic Alloy Thermal Interface System
Enerdyne Solutions (PDF)

Excerpts
http://img.techpowerup.org/060502/IHS1.jpg

http://img.techpowerup.org/060502/IHS2.jpg

http://img.techpowerup.org/060502/IHS3.jpg

http://img.techpowerup.org/060502/IHS4.jpg



Chris G. Macris

Mr. Macris, co-founder (of Enerdyne) and CTO, has 13 years of experience in research and engineering design, intellectual property development, entrepreneurship, and business development and management. He is active in several professional engineering organizations and is highly regarded for his scientific acumen and broad industry knowledge. Mr. Macris previously founded and led Xavier Technology, a provider of computer network test equipment. He holds 7 patents and has 2 more pending. Mr. Macris has a B.Sc. in General Science from Seattle University.

Re: T junction temp
 

hmmm a number of iregularities and are there any actual results?

Not exactly sure what the FEA analysis is trying to prove, and it looks to me not to be bullet tight.

Re: T junction temp
 

Enerdyne Solutions makes the Indigo thermal package
it was a competitive analysis of current technologies and was presented at the
International Microelectronics and Packaging Society (IMAPS) Advanced Thermal Workshop in 2005

the paper from the previous year was
Performance Reliability, and Approaches Using a Low Melt Alloy as a Thermal Interface Material (PDF)

a results summary can be had here
Indigo Thermal Impedance Comparision


but the pertinant passages I thought where
"These differences can be factored out by application of a TTV-to-CPU correction factors"

test rig diagram & proceedure

"small changes in the package dimensions from Oil canning or spherical deformation can be significant, The Coefficients of Thermal Expansion (CET) mismatch between the Flip Chip Pin Grid Array (FCPGA) and the heat spreader lid may cause the Bondline Thickness (TIM1) to change slightly as the package temperature is lowered from the adhesive glass transition temperature (tg)"

"This small dimensional instability is not normally significant with low performance Thermal Interface Materials (TIMs)"

implying that while care must be exercised in the selection of TIM1\IHS\sealant when taking into consideration oil canning,
the impact on TIM2 is less pronounced do to its lower conductivity and that maintaining an optimal contact between the IHS and heatsink is likely targeted by package designers to a specific temperature range. (observation of the "flatness" of an IHS is really dependent on its temperature) far more than any compression flex, and further that an "optimal target temperature" is unlikely to match "enthusiasts" and especially extreme "coolers" but rather be the median temperature youd see in a server or desktop possessed by the average joe.

further investigation of the papers shows the considerable weight maintaining the seal plays in the reliability of an IHS
by deduction also temperature\thermal cycling dependent

Re: T junction temp
 

Resurrecting the devil with some possibly valid to the point links here... don't expect discussion to continue, but links may be handy in amongst the "reference library" that ProC is...

http://www.coolingzone.com/Content/L...ay1999_05.html
http://www.coolingzone.com/Content/L...ep1999_05.html
http://www.coolingzone.com/Content/L...ay2000_05.html
http://www.coolingzone.com/Content/L...Sep2000_5.html

(Good index here: http://www.coolingzone.com/Content/L...Papers/#Theory)