Is this thread about IHS discrepancys now? hmm.
Well from the pic it is conclusive that the internals are predicable and were in fact predicted correctly. Nothing big here. Not even accelerating inlets

OK, here is the shot of the Apogee base plate I promised... :)

http://www.leesspace.com/images/Web_.../Base-Pins.jpg

Note there are 12 rows x 17 columns = 204 pins (water flow is from side-to-side in the previous pic)

http://www.systemcooling.com/forums/...16&#entry32916

looks like the same as the MCW55 to me,
less the ridge which dropped the head loss
??
I guess the CFD was to arrive at the 3mm bp thickness, not to assess the pins

for, ahem, the designed flex
what crap (can conduction losses be differentiated from 'compliance' gains ?)

otherwise they know how to test, should be as described

had not thought so thick, 1.4 is a good % of 3 and indeed thicker than several
interesting, compliant bps are NOT part of any sink spec and generally a very bad idea wrt the internal TIM joint

Thanks Lee, a review in the pipeline ?

Ah crap, got a headache now! I'll print and read over the weekend.

On one side we have debates over spreadability, and on the other we have actual temp measurement. On one side we have repeatability, and on the other we have actual CPU temperature simulation.

Hummm..

Is 1.3-1.4mm the over all thickness or the thickness over the die? 1.4 seems like the over all thickness and not the thickness removed to fit over the die. Unless Intel does it different then AMD anyway.

Yes, but much testing and understanding needed first... :)

I mic'd the base plate as being .120" (~3mm) thick as Swiftech says (bottom surface to base of the pins). Total thickness is .276" (7mm) from bottom surface to top of pins.

The flexing of the wb base-plate is exactly what is required to cause the Intel TTV to read incorrectly, and this was demonstrated to very dramatic effect with another block. That it is acknowledged that the bp flexes, thereby NOT pushing the IHS against the heat-die in the center where the thermal probe is located, is exactly why I believe that this methodology of testing is flawed.

The wb is being manufactured to provide low temperature readings on a flawed testbed by exploiting the very same flaws that were observed to give erroneously low results. The data is the result of a system error.

we shall see

Hmm this thread points to one of my dilemmas:

I dislike IHS in principle and pop them off my own CPUs. But for the test system I have left it on because I figured twi (testing whilst intoxicated) dictated I'd eventually break something otherwise. I also figured that popping it off precluded testing any "normal" mounting stuff.

Did I err? Either way I go with that I'll get shit I think.

Ok, it's been announced now.

Well you have to leave it on simply for mounting issues if nothing else. I think this whole base flexing thing is shit myself. Bill suggests it is PR BS yet Roscal claims Swiftech is honest. The two don't add up. Then there is the TTV issue Cathar brought up which is hard to dismiss.

I am going with the die sim as I am more interested in actual performance as opposed to system performance. Let's face it, it dosn't matter what top 5 blocks you use they will all be well within the error margins of the onboard temp monitors not to mention mounting issues and flexing IHS and bases and blah blah.....

Hmm if all 5 top blocks are close together in performance on a die sim then mounting issues on motherboards and "tippiness" and cost and even appearance become even MORE important to look at, right?

Another of my dilemmas

I'm pretty sure "succeeds" isn't used properly in that press release. They mean "supercedes" I think.

//end grammar nazism.

I would use succeed in that way.

Heck: "To come next in time or succession; follow after another; replace another in an office or a position: She succeeded to the throne."

They put the 600X in "discontinued products", BTW

I was meaning more torwards the end users results with the top 5ish blocks. Their results are hardly going to be noticeably different providing they mount the thing right. I think most significant temp drops after using a new block are more from a better mount as opposed to actual block performance.

However the 5 blocks (nopt limited to 5, just a number out my ass) performance on the die sim is still pretty damn close. To close to measure accurately from the average Joe.

Also IMO 1-3C means jack and I think more people are caring less about the absolute best they can get because they end up spending $300 for a block that gains 1-2C yet their overall system performance has not noticeably changed. That $300 could be better served on more memory, vid card, faster CPU ect...

I personally think this Apogee block (providing performance is as advertised) is kick ass. Low restriction, high performance and priced well (not to mention I am a pin grid fan boy). Looks are the only down side I can see and it looks professional, appeals to me, as opposed to bling which the average enthusiast seems to be after these days.

Anyway I am way to tired to think.

Quick example before I got to bed.

According to pH previous results the difference from the Storm G5 and the D-Tek white water is 2C at 1GPM and less at lower GPM's.

I have no idea what the G5 ($over 100US?) runs but the G4 is not much different than the Swiftech Storm which now can be had for $50. The White Water can be had for $29 at cooltechnica and $34 for the universal top version.

Now.. before I sound ridiculously like a moron. I would just like to ask.

How is the Apogee's design enable so called better temps than the Storm?

It looks to me as if the Apogee is a high flow block...

so the TTV setup is flawed? how is the TTV test setup less representative of our application than the "other" (copper die) setup? or is there a discussion on these forums that I missed?

if the TIM joint (inc IHS) is poor, then should it be ignored? if the TIM joints (still including IHSes) are inconsistent from the factory (as is widely reported on forums for AMD's processors), then it should be tested and stastical variances quantified. no?

Thank you JD, my thoughts exactly, I have a feeling I will be quoting that alot in the forums.

PR and marketing hype to take advantage of the thanksgiving weekend. Do you all forgetten about it? Also think about what comes a month after thanksgiving.....

How long do you think it will take for think independent test data will come to verify these results? Even when it does do you think all the noob will care if the results are 1-2C off. If it's less than 2C, lets say 1.75C, most of these people wont care. It won't even show on MBM temps.

Swiftech will just say " should be added that under certain circumstances, the Storm water-block may perform better than the Apogee water-block. We cite for example earlier generations AMD Athlon XP, MP and Duron processors where the die size is smaller in surface area (100 to 140mm2) than current microprocessors. In such instances, the difference in temperature was found to be 1.4°C at 100 Watts, and at the maximum flow rate allowed by our test equipment (about 3.3 GPM for Apogee, and 2 GPM for Storm). Such test were conducted using the alternate testing procedure described in the link below."

or claim differences in error and testbeds.

I just don't see how they just condensed the design of 5000-5002 series and got results better than Storm. I think they would get temps similiar to cooltechnica blocks @ 1c higher than storm but with better flow rates. I mean squares and diamonds are pretty similiar and i bet cooltechnica tried many designs. I see why they got the rights to StormG4 though, no competition.......

The TTV setup does not monitor the actual die temp, just the IHS surface temperature.

If the wb base-plate flexes, along with the IHS, and I can assure you that CPU silicon is flatter than a very flat thing, then the heat-flux pattern between the die and the IHS is changing with respect to that flexing. Naturally, if the block is flexing and therefore so is the IHS, then the IHS is not being pushed flat against the CPU die, and so the heat distrubution between the CPU/heat die and the IHS is now different. Since the thermal probe is merely measuring the temperature of the IHS surface, its readings are therefore going to be affected by any flexing.

IF both the heat-die center temp, AND the IHS surface temp were known, then I'm almost 100% positive that we would be able to witness and quantify these effects.

As it stands, the temperature of the CPU die / heat die is not known, yet it seems that some people are willing to dismiss this as being irrelevant.

I have been privy to data generated on the TTV that defies logic in terms of the TTV's accuracy when base-flex is present, however the data is not available for public consumption. If only that data were available for public consumption, then the true picture of what I'm describing would be laid bare for all to see.

Market forces being what they are, however, prevents such disclosure.

If the heat-die temperature were being monitored as well, then the TTV would be representative of CPU temperature, and would therefore be more suitable.

Exactly my argument. If such is not measured and is not known, then how can one confidently state that there is no systemic error present?

Jaydee > 1.3-1.4mm is equal to H on this pic (measured on a real IHS) :

http://membres.lycos.fr/roscool/forum/ihs.gif

why can't anyone grab the Apogee, slap it on the cpu and test the performace? Then switch it to Storm and report the data?

Because you need:
- knowledge
- and equipment

Most people dont have enough of the former and dont have the proper of the latter.

Thanks Roscal.