Someone remind me if the Intel TTV uses an actual processor, or that crazy ~2" diameter heater element.

sort of like a processor?

http://developer.intel.com/design/Pe...s/30056401.pdf

Appendix E

post #173
both guesses are wrong, treat it as a 'black box' designed for its purpose
answer your own question: why would an exaggerated heat source size be used ? (again, consider the purpose for the heat source)

Orkan
old version/setup, but generally similar

-From a designer perspective (i.e. reticular implant), I would expect different performance, but it could go either way. Too thin a bp could be detrimental. Optimal thickness would be better, but specific to a flow rate.

To quote the textbook:
TTV fuzzyland all over again.

This data shows promise of an actual replication of a core. Is it so?

Ok will go with "blackbox".

Holy smokes; just realized that the proposed groove for thermocouple routing is IN the IHS (page 68).

welcome to the party Ben
so a tester will groove the CPU used as a heat source/overclocking basis and bond in a 40ga TC,
not a die temp but perfectly usable (the scale will be compressed compared to the silicon temp)

EDIT
it just occured to me,
do you guys understand that the Intel thermal limits are based on the case (IHS) temp ?

this die temp stuff is not necessary to effective cooling as such is a consideration in package design, for thermal mgmt Intel defines the case temp as the basis of many calcs (AMD grooves the sink so their reference is the other side of the TIM joint, the sink or wb bp - probably a relic of their bare die days)

I have described an acceptable IHS heat die setup multiple times. Seems some people are too busy hanging shit to notice it.

I've gone beyond the point of caring now. Snide asshat comments have destroyed for me any illusion that I was talking with people who have anything less than a politically oriented motivation for their comments.

I'm out. Totally.

I've arrived!

Ran a quick cal of the 85% uniformity JEDEC requirement; all is well, from a contact area perspective (96% contact over core area, based on 14mm square core).

I did. Worst case too, which gives us overclockeability. :D

Agreed, AMD needs to catch up.

Ah darn, now I have to pickup Stew's case (no irony, will actually do).

Later today.

I wouldn't bother. Just wait for independent test data.

Will be interesting to see the fallout when that occurs, whichever way the cards fall.

Was referring to data that you know that I don't have the permission to publish.

You always knew that though. Too busy constructing snide comments it seems.

Said data projected a unit thermal resistance lower than that of the inherent thermal spreading resistance of the copper in the unit.

Just wanted to make that point clear before leaving this.

agreed, no hard feelings - its about testing

At the end of the day... I doubt switching from apogee to storm, or storm to apogee would grant one a higher overclock.

Independent testing? ... ... ...

A forum full of people that are considered industry experts can't even come to a conclusion about how to test a block correctly.

So who is going to do this "independent testing?" Hell... maybe I'll buy a block for them so they can put this crap to rest.

Orkan, as much of us like to bitch and moan about things like testing, it is difficult to do properly... there are only about 5 such people that can do it right for the most part. We are indeed splitting hairs here, but why not :D I hope pHaestus will indeed do some tests, although by the tone of his post(s) it doesn't seem promising. I think Lee (robotech) will do a test and then hopefully JoeC (although, his data can be whacked). If we get 3 tests from these people, we can start to see a clear(er) picture of what is going on and how reliable or not the TTV is or is not.

Cathar, not according to my analysis.
When R=C/W
where W=total heat dissipation through all of IHS
C= Local IHS Temp-Coolant Temp
which is the definition used for TTV testing in July 2005 pdf
W distribution will depend on heater/heat-die dimensions and thermal characteristics and to a,probably, lesser extent the cooling properties of wb.
The case Post133 illustrated was a uniform flux 1x1cm die with 0.33x0.33mm Local area Temp(width of groove 0.33mm)
For 270,000w/m^2c on 14.4x14.4x1mm case
A tapered Flux Channel 14.4x14.4mm >0.33x0.33mm
Cu Resistance=Total Resistance- 1/h(eff)A =3.57949 -0.017861=3.561628775 c/w (Waterloo
This resistance with reference to a 0.33x0.33mm area
Translated to 1sq cm ref area this is 0.003879 c/w
This a major part,but not all, of the total Resistivity of 0.003898c/w/cm^2

Edit Corrected pdf date to 2005

hmm - is that not the implication of the hypothesis that the lower IHS temperature results (partly?) from a different block geometry leading to poorer IHS to Die contact?

(assuming it is the efficiency of cooling the die as a whole that determines the o/clock... rather than better cooling of hotspots etc.)

if you look at the "actual CPU testing" figures swiftech link to just before the graphs on the apogee page (which are for a dual a64) then the storm figures give an IHS temp that is (slightly) lower than the CPU probe in each case, and for the apogee the same or (slightly) higher than the CPU probe. that seems to suggest that there is certainly a possibility that the accuracy of an IHS temperature as a proxy for die temperature may vary between block designs....

Les, I was not referring to the Apogee data when talking about defying physical possibilities. That comment was referring to data of a tested waterblock that I cannot disclose or reveal the original data.

Fully aware
I have no problem interpreting the " data that you know that I don't have the permission to publish" in the same manner.
Suggest you review your analysis

We shall see.

*continues eating pop corn while reading the must intellectually demanding thermal testing soap opera ever*

lmfao

hey man... pass the butter/salt

Ssssh, no talking, I'm trying to listen and understand what they're saying.

Listening is easy. Understanding is hard. Learning is what its all about. :)

I know this horse is more than dead, but this strikes me as particularly concerning. Note the highlighted section, taken from HERE bottom of page 77.

http://www.anonforums.com/builds/ttv.gif

aww man, I was hoping it had unlimited reliability and was future proof to simulate intel's chips well into 2010.

Also note that not all I-TTV's are created equally. Intel appears to make specific TTV's for each particular CPU (the stated resistance is typically different between models). I don't know what TTV Swiftech is using but I suspect it is one of the newer versions, possibly even modelling a dual core CPU???

Scott and Lee, you are referred to post#183
there are many things I may not discuss
please do not assume that because you are not told, that something stupid was done by Intel, Swiftech, or myself

why would anyone, having gone to the trouble to make a dual core TTV we will assume, then use it to replicate a single core - when such single core TTVs already exist ?
- apply this to Intel, Swiftech, and the guy doing the testing
all incompetent ? possible, but not probable

Scott
I accept that your questions are genuine; each model improves on that before
if the tool were so flawed, do you not think that a better one would be developed ?
you are assisting in the 'condemnation' of a test method about which you, and clearly Cathar, have no experience and little real info
I am unable to do other than share my experience in a general manner

it is rather strange that the only 'info' accepted w/o question is from Cathar, who has ok testing (we accept) but no hard data sets at all
yet those who do provide data are subjected to claims of bias, stupidity, incompetence, etc

Lee
I wish you luck in dealing with the IHS issue
there seems some (considerable by those who do such) anecdotal evidence that the AMD IHS/CPU TIM joint degrades with repeated mountings (and thermal cycling if sub-zero), I have not heard of this issue with Intel CPUs (anyone ?)
-> so if you use an AMD CPU, how do 'we' know its TIM joint was/is ok ? (how do we measure 'ok' ?)
I would suggest that a before and after test be defined to 'qualify' the internal TIM joint to eliminate this question (raised by Cathar and does need to be directly addressed)
it you groove your CPU, you could then play head games using all the different CPU temps available for a rainbow of C/Ws (of course W is not known either); a pissing contest par excellance (which I KNOW is what you do not want)

you will have difficulty 'selling' bare die data to IHS users w/o defining the correlation, a task I would not assume
perhaps better to present bare die and IHS data separatly, the user selects that which relates to their actual application

realism never hurt

Good question hereby exemplified - we get frequent cases of NEW as well as 2nd hand / subjected-to-frequent-mount-and-dismount CPUs exhibiting ridiculously high temps on a setup that with the same model CPU formerly produced much better results. Repeat mountings showed no evidence of solution. Removed IHS, and resulting temps beat the hell out of the previous CPU with IHS that exhibited peachy temps.

ie: (worded better) Storm G4, D5, HE120.1 and some unsuitable fan. All variables constant (ambient, liq temp, flowrate, pressure, airflow etc)

[3200+ sample A] under load at 38 deg C. [3200+ sample B] under load at 49 deg C. Cooling system not changed. CPU is only change. Repeated mounting to elliminate. Only point that we have no control over is the IHS > Die joint. Remove IHS from [sample B] and temps become sound. Better than [sample A]. Remove IHS from [Sample A] and temps match [Sample B]. The only establishable flaw - IHS. Becoming more and more frequent round here, and we only handle AMD CPUs. Very rarely ever have an Intel CPU coming thru our doors. Lucky if more than 5 a year vs a massive quantity of AMD in comparison.



Thus I tend to assume watercooling market is predominantly AMD based. Or enough so over Intel users to warrant testing being done in preference on AMD based simulation rather than Intel.

Don't have experience of Intel IHS flaw rate to compare. Did you gain any info on sales levels whilst at Swiftech Bill, Intel blocks vs AMD blocks?? Universality of Storm rules it's sales levels out form being useful, but 6000 series would be... Is my assumption based on our sales reflected elsewhere by anyone else (block manufacturer would be handy here - DD, Swiftech)? It's at the point where we literally don't consider Intel at all in any of our equations... technical, sales, purchasing or otherwise. This is over 9yrs of sales at highstreet component level, highstreet off-the-shelf PC level, and online via enthusiast aimed online store.

Indeed - if no solution can be decided upon, simply (?) do both. Satisfies all arguments - before folks fall out past point of restore, which no-one wants. *passes round the chocolate biscuits*

However, those results only self-comparable unless all have access to same TTV and same Diesim - or correlative formulae provided to calc. Back to the same old worms... new can.

Stew is a source of 1st rate chocolate biscuits

cannot comment on sales, but Intel is not to be ignored
not everyone will pop the lid, that being said the longevity of an Intel CPU is worth considering - which apparently some do (?)
I do not use CPUs as heat sources, but were I to do so it would never be an AMD CPU due to the IHS TIM joint
- CPU heat is just heat, source size/TIM joint only difference

I have burned up early TTVs, I have never had an internal TIM joint separation, but I have sucked bonded TCs out of the groove while removing sinks (and pulled sockets off the board !)
the IHS succeptability to internal detachment depends on the TIM material, an AMD problem I believe (could be wrong, eh)

BTW, IF IHS detachment is an AMD issue, wth is all this Intel TTV crap with no known instances of a TTV debonding ?
'what if' is such fun

let me add something to the CPU IHS grooving discussion:
the IHS measurement in conjunction with the 'internal' CPU temp (any source), plus the bogus Watts, can establish a ref C/W for the internal TIM joint,
its degradation can then be tracked (no help if an initially 'poor' TIM joint though)

would work for any CPU with an IHS,
but I still would not use an AMD CPU (unless bare, which testing I do not do)

note that I initially drilled all wb bps, I have measured a lot of TIM joints and I distrust them as much as Cathar; huge sources of variability in every installation
and if degradation of the internal TIM joint is occurring, . . .
what is the point ?
cheaper I guess, if OCing is a hobby then CPUs are consumables

this last point leads to another conclusion:
if an enthauast uses an AMD CPU, it should ALWAYS be bare (else the performance 'advantage' is illusory)
??
(another made this same observation several pages ago)

No Bill, I do not claim stupidity or incompetence at all. All I am questioning is the TTV and its reported data, not the integrity of the people doing the testing with it, let's get that clear. I can appreciate those detailed things which you can not discuss. I am also very happy that this discussion has stayed somewhat civil, as I have said before there is no witch hunt here, we just want anwsers as does everyone else. Bill, if you can answer good, if not I understand; were any of the TTV's that were used socket 775 with the newish IHS as opposed to the old brick style IHS?