CPU flatness and TIM joint materials
 

http://www.electronics-cooling.com/h...bruary_a1.html

my 'looking' at amb temp is probably useless
(and I'm sure not gonna heat up my optical flats)

Bill
Know little about CPUs but don't AMD come in two flavours - ceramic and plastic. Have you looked at any other than the ceramic Duron yet.
BTW my copy of Feb. Electronics Cooling arrived last week.

I was under the impression that AMD went to organic packaging for everything what, a year ago ?
in any case Durons are no longer in production (I believe ?)

and I doubt that the CPU backside (our topside) 'distortion' at temperature is different between the two

sh*t, more questions than answers
hi ho
- this is speculation, no way to verify

Durons are no longer produced, that's correct.

That brings up more questions indeed. given that the heat is not uniform over the die, this bowing effect probably isn't terribly uniform either.

The article mentions variations in the order of 25 um, and 45 um. First hand, I'd be tempted to say that adding excess thermal material (see attached, red highlight) might allow the gap to remain filled, but I don't believe that that's relevant: the gap variation may add a significant variation in the TIM joint's properties (or does it??).

If I was in your shoes Bill, I'd be taking a look at your die simulator: you probably don't experience any warpage, so your tests should give a "slightly better than real-life" figures. You might be able to re-create the warpage, by capping the die with another material, but it'd have to be bonded to it, and produce the same kind of warpage... (I'm glad I'm NOT in your shoes!:D )

Some relevant Coeffients of Thermal Expansion

Material CTE (ppm/deg-C)
aluminum 23.0
copper 17.5
solder 25-26
FR4 18-25 (Fiberglass AKA organic substrate)
ceramic ~6
silicon 2.3
underfills 19-35

not really of import wrt my testing, as it is all relative/comparitive
-> as long as I keep it the same

I have long said this:
do NOT assume for an instant that Intel and AMD do not understand completely what is occuring
and it follows then that their designs reflect this understanding

there are no oversights, no lack of attention to detail
(Intel's past Pentium fiasco notwithstanding - they just thought they 'could get away with it')

I suspect that in this case, the detail they find most important is manufacturing cost.

try reliability
a much better 'fit' I think
if it doesn't work, the savings are quite moot

(or were you referring to the P fiasco ? I think that was a marketing decision)

I don't know if you saw this article that I linked some time ago in another thread.

It is my impression that if the manufacturers were going for maximum reliability they would still be using ceramic substrates.

Ceramic - Silicon ~ 3.7 ppm/C difference in CTE

FR4 - Silicon ~ 19 ppm/C difference in CTE

Of course with ceramic, there is more stress on copper/ceramic interfaces, and shearing of vias within the substrate may be an issue? Lots of tradeoffs here.

Bill,

Just 're-noticed' this comment from your Waterblock Bench Testing Results article.

Die flattening with increased temperature reduces the thermal resistance of the TIM joint?

my 'die' is Cu,
actual deformation due to a deltaT of 30°C is not known - but not presumed to be too significant
(a sq riser from a larger block, the heater being the width of the riser)
- and any thermal deformation appraisal must of necessity also look at the wb bp, each of which will be different

note that the article looked at a much larger deltaT

Ahh. Right. Wasn't thinking.