Cooler testing
 

Ok guys I have my die simulator drilled and ready but need to insulate it still. I am thinking the tiles they use on furnaces may be the best bet for this. I also need to measure both current and voltage simultaneously while testing: Is a good DMM acceptable for this?

I killed a TBredB 1700+ that did 2400MHz last night trying to solder wires to it. The ground wire got somewhat out of position and when I forced the chip into the socket it exposed bare wire. Ground to CPU pins = not the best idea. I did dig up a 1200MHz Duron; gonna have to make do with that for now.

Another AMD goes to the great water-cooled super computer in the sky – I have sent quite a few myself. Do you have any pictures of your sim?

He might be replacing it with a spare 2000+ I have... 0151 hehehe rather old nowadays :D.

Last one I killed was a Tbird 2100+. I am going to buy an opteron as my next CPU but I am waiting for the price to drop a little. Which reminds me pHaestus do you have a way of adding a integrated heat spreader to the simulator to better simulate the new CPU’s or are the results going to base on the older exposed core CPU?

FWIW.

Bill used a phenolic resin, in his first die.

I'm also getting close to getting my heat die going. I've been looking at the option of not only insulating it, but using the air pump built into my chiller, to remove the air between the heat die and the insulation walls. Still needs work...

Ben, you might actually want to keep that air in there... air is an extremely good insulator.

The simulator is basically the same as the one JoeC uses at overclockers except I had #rotor drill me two holes for cartridge heaters into it. I am aware of the phenolic resin but not sure if I can buy it locally or not. It is not a big deal to put a bit of thermal paste on the die and then add an IHS to it. IMO that's a better choice than milling a larger die anyway.

??
since C/Ws are specific to a test setup, why bother ?

BTW, the 2 TIM joints do not have the same thermal resistance
I canna say more

...and the lack of air is an even better insulator. ;) The problem is that I don't know how powerful the suction is. Plus, It has to be reproducible, so I have to add a vacuum gauge, and see what the max suction is, then throttle it back a little (in case the pump fails, or wears). I'm just not sure I'm willing to go that route, yet.


I'm also stuck with the choice of the IHS. Without it, the die would be ~13 by 12mm (156 mm^2) (thanks to a tip that was PM'd to me), and should closely resemble/reproduce a P4 (square, 146 mm^2), and an Opteron (rectangular, ~164 mm^2).

(I still have to confirm all the dimensions above)

After Bill's comment (of which I was already aware), I'm thinking about dropping the IHS alltogether: I don't believe that the "heat spread" is significant enough to warrant all the extra effort. I believe that it would be a greater source of error to use an IHS. In my case, I was going to build a second heat die just for it.


pHaestus, where in the die are you going to place your temp probe? I'm tempted to reproduce the AMD spec for HSF.

I assume you mean resistance per unit area(Specific Thermal Resistance?).
"Canna say more" = "Not allowed to say more"? "Canna say more" ="Dunno"?
If "Dunno", would you suspect that it may be the effect of the different pressure or some other phenomena.?

NDA

I have to agree that using thermal paste to add a I.H.S would better simulate an opteron or P4 etc. Now I wonder since we agree on this – is it no longer an opinion but a fact… :eek:

Would it? Is that what we are doing is trying to simulate die's? If so, why? The die changes watt output constantly and inconsistantly so whats the point in trying to simulate it on a die sim that has a constant watt output? Even if you match the size of the die on a certain CPU your still in no way simulating it because of the power inconsistancies and even hot spots. The die of a CPU isn't an even temperature like a die sim.

I say just use the die you have and be done with it or you going to open up more problems than you can control IMO and loose considerable accuracy in the process of trying to control it.

I don't know though you guys probably know better than I....

huh ?
only you and Ben
facts are not based on popularity

the whole point of using a simulator is to get as accurate C/W and flow vaules for a block. it's the job of the user to then match his rig's equipment and CPU to the results of the testing and see what kind of performance can be expected. simulating every possible CPU, or only one for that matter, will make it harder to adapt the data to your perticular setup. at least that's how i look at test results, you guys may have a deeper understanding of what's going on.

You are right Jaydee every time you add a TIM you affect reproducibility of the mounting for sure.

I see... I thought you meant removing the air so that the insulation would stick tight to the die simulator. The method you are proposing would indeed be superior.

I think you guys are missing something. If the masses move to an IHS on the core, and the testing is still using a die sim for cores... how is this beneficial and directly related to the customers equipment?

It seems that if you place an IHS over the core replicating what the users have, wouldn't that give you more transferable / realistic results??? People mentioned 2 TIM joints... well... isn't that exactly what every user with the new IHS is using?? If you guys are more worried about mounting variables rather than simulating the chip then something's wrong. Back up.. attempt to replicate the chip.. then attempt to find a way to remove the variables. If someone is making a die sim without considering the IHS, they are attempting to only test yesterdays scenarios.

just a thought. :dome:

Winewood:

1) Bill just said that the IHS does NOT behave just like a second TIM joint. As he is under NDA, one would conclude it must work better than predicted from such.

2) Test benches are just that: controlled tests. I would assume that a smaller die in general will produce higher temperatures than do the chips with IHS. I would also assume that the CPU + IHS produces temperatures higher than a die simulator the size of an IHS. Better to err on the high side for performance than on the low side right? Plenty of inflated performance as is.

3) How my heat "spreading" does the IHS actually do? Any data on this? JoeC seems to think the answer is "a ton" and my guess would be "a little bit". We do know that temperatures drop noticeably when the IHS is removed...

All I am saying is the use of a smaller die may not be such a bad idea even in the age of the IHS.

Right.

What it comes down to, is this: can we reproduce the heatload from a processor, without using two TIM joints. (no Bill, I'm not in la la land, read it again).

IF, *for example* I use the 12 by 13 mm die, I'm already off a little bit in perfectly replicating either a P4 or an Opteron/Athlon FX, because the dimensions don't match perfectly.

Then the heatload is going to be distributed differently from the die than with the actual processors, further putting me out.

But the IHS is still going to transfer the full heatload through an area that's almost identical to the size of the core, albeit a little bit larger, because the IHS is pretty thin: it's more of a protection to prevent core crushing, than an actual heat spreader.

So...

by doing away with the second TIM joint, it reduces a significant variable in my setup, and I'm still reproducing a CPU heatload reasonably well, plus it's a bit easier to reproduce: TIM joint can be somewhat subjective.

So I can them measure the block's performance without having to figure out two TIM joint variability. (Well, actually, I still have to figure it out, but it's simpler).

The result is that you know how well you can expect a block to perform, because you'll have a C/W figure that you should be able to use.

The real question is: how am I going to take the temperature measurement, in order to get an accurate reading? The second TIM joint would normally add a few degrees.


AMD specs for measuring the temp within a heatsink, call for a 1.5mm diameter hole, whose center is 2.2 mm from the base. The heat die is going to be different, but how?

BTW, AMD specs now call for a thermocouple to be mounted directly on the IHS, and the HSF to be notched to give room for it.

Ok.. it doesn't. Then is it for the worse or better? Didn't say.. can't derive from no data. Bill wouldn't accept no data understanding from others. You can't even determine to what degree or extent the difference. So, what is that telling us? nothing. I could say, the the cascase and lrww don't behave the same.. does that tell you anything?

Lets argue this point slightly. I have a pin size block and a lrww. Both will not behave the same on a simulator of a core vs. one with an IHS. The pin style block may not look good at all compared to a lrww on the core sim. Now on the IHS it may be very close. Why??? the lrww was made to a narrowly defined core hotspot. The pin would work much better with a spreader than would the lrww as it can work better with larger area heat sources like.. a TEC. However, we are not talking TEC cooling now, but IHS cooling. Are we cooling die's anymore?? In a way... no. We are cooling IHS's. Why are people afraid to change to the market?

Now you have testers with the core modeled heat die's, and everyone now is using the IHS. Can you really tell them how their block works with an IHS? Or are the testers just using a core because you like the pretty numbers? Take a die sim using a core heater, then place a IHS on it. Isn't that much closer to real world testing now than pretending the IHS doesn't exist?
If you know there is a difference.. or assume it... then you must account for the changes in your sims. You know they aren't the same. You said it yourself. We wouldnt use a core to test a TEC cofiguration, because the core can't replicate the TEC surface or heating element. Why do it in this case...?

There would be nothing wrong with the numbers obtained using the core only simulator. The only problem I have is when these numbers are used to represent real world CPU’s with I.H.S results. Present core-cooling blocks concentrate on cooling a very small area. The area of the core is about 10 mm by 10 mm or so and centered on the CPU C.W are based on these measurements. So what can be said about a spot cooling blocks is that they can cool are very small area but that is it. A pin block is still a spot cooler only the area it cools is much larger (usually the area of the CPU). What this say’s is that if the core was moved to the top of the CPU the current direct die cooling block would seize to perform if not fail completely. Do the same with a pin style block and the block would still have a very close C.W if not the same it did while the core was in the center of the CPU. My point is this; adding a I.H.S is like moving the die- Don’t expect current performers to remain such and ignoring the I.H.S in testing is only skewing results.

Intel says there's a temperature difference of up to 8C from one point on the P4 to another. Must we simulate this as well? Your assumption that the LWRR performs significantly worse on an IHS-equipped CPU is based on what? The desire to argue? If the IHS doesn't transfer heat laterally as well as it does vertically then the effective cooling size may not be so much different than on a bare CPU.

Do you not understand what an NDA is? Bill CANNOT say more but he is telling us we are on the wrong track. That's more than I see anyone else under Intel NDA doing. This isn't the first time you've gotten argumentative when Bill refused to disclose info that is proprietary.

Looking at the numbers on overclockers, I am not seeing a huge difference in the relative rankings when the P4 vs AMD die is used. The C/W are lower because the surface area in contact with heatsink is so much greater, but the same basic ranking prevails.

Am I sensing that the prevailing opinion is to not even bother with testing if I am using an AMD sized die?

I understand fully what an NDA is. Am I arguing that hes not forthcoming with information... or the people attempting to derive conclusions from no information!??? Its the LATTER. You guys derive WAY too much from the air here.
errr.. the information would come directly from .. Cathar. He stated that his block wasn't designed to be used with a TEC and it was.. per his design only to cool the surface the size of the core.
As for the temp diff across the IHS, placing a IHS on a core die sim would come much closer to "simulation" than disregarding it because you guys aren't willing to account for it..
EXACTLY! is joemac the only one who can see this?? It seems that some past understandings or notions may be controlling judgement a tad more than thought..

But don't let me sound angry.. in any form I am not.. just want testers to accept the environment they are in now. They are afterall testing tomorrow's blocks, not yesterdays...