The wafers that I have dealt with have a thickness of 725µm. This is not necessarily standard, but it'll be in the ballpark. The various metal, oxide etc layers, ~6, would add up to not more than about 1µm so you can disregard them.
It does not matter where you put the element, as long as the whole is well insulated. More important is the thermistor placement if you want a measurement comparable to a CPU. My tests with the flux block show the effective L of the die PLUS(!) TIM =2.65mm of copper in my case, a total C/W of 0.062. This doesn't help much but it suggests that the silicon is thinner than you think. 0.4mm would not be a bad guess I'd say.
Possible hint: use two thermistors with a known spacing in line with the load to water path, a la "fluxblock". Then you have the gradient. And hence a second power measurement to back up your voltage/current calculation.
Cheers
Incoherent
|