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Unread 05-22-2004, 09:19 PM   #33
Starman97
Cooling Neophyte
 
Join Date: Oct 2003
Location: Austin,TX
Posts: 27
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Quote:
Originally Posted by Jabo
Right, what I meant was that net size is bigger BUT process is getting smaller and density of elements rises leaving any possible channel dims extremely small.

* The channels are cut into the bulk substrate, not into the region of
active junctions, which is extremely thin, 1000's of angstroms..

For CPU to work it has to be an intgral structure so it is not possible to create micro channels between layers of circuitry. Having die microchanneled on external surfaces is counter productive and makes no sense.

* nonsense, micromachining structures with active logic is commonplace
They wont go beween active elements though.

Even if it was possible/feasible to make a die wirh layer of circuitry stacked on each other with micro dim spacing inbetween with some sorft of interface connecting them (uff, nice bit of SF going on here) then amount of coolant types described by you needed to pass through to achieve any cooling would
call for extremely high pressures (to maintain coolant's velocity or mass flow in time through changing diameters of a vessel pressure needs to change - some basics here for ya d00de) = kaboooom and flying silicone

* Look here: http://www.darpa.mil/mto/heretic/pro...georgia-4.html
4.5 PSIG, that's nothing to Si. the internal stresses in the die are far greater than
that caused by pressurized channels in the bulk substrate.

*BTW, they are stacking transistors in production devices, I've even seen
stacking of dies in prototypes. They grind down the back of the die and
cut holes into it to connect circuits between the dies, then they fuse the two
dies together in an annealing process. It's expensive, and only goes into
expensive products where space is at a premium. (Mil stuff and sensors,
but it's soon to go into power controls. Put a micro ontop of big power FETs)

Read about thermoelectrics and use of electrons themsleves for cooling and go down to nano level of architecture

* that's another approach,, more advanced than micromachining to be sure.
After all, it is the diffusion of energetic electrons that moves heat in things.
The trick is to get the hot ones to move out and the cool ones to move in
while inside a solid state material.

Skimmed over your linky. It looks like an attempt at direct die phase change cooling using premanufactured on-die-surface-microfinns... I could not understand why did they limit themselves by putting a glass cover on top of this channels severely limiting the amount of coolant to be boiled and they use sequential flow pattern.... then check page 35 for test results - useless performance for current CPUs thermal output Nice find anyway, I hope I'll fbe able to find some time to read it all
The chipmakers ARE doing work on this right now, a lot of the sources I've
quoted are a few years old, the tech has been taken into the research labs
at the big semi makers, Semetech only does the initial research, they dont
productize things there. Intel, Moto, IBM,AMD are all working on this and keeping
quiet about results so the others dont patent the designs out from under them.
It is the only way to pull 200W/cm^2 from a die, you need mass flow to move
the heat faster than internal thermal diffusion.
Even if it's just to a copper cap that is the size of the external package.

I've seen the presentations on this back when I was at MOT, they havent
given up on it.
Here's an Intel paper..
http://www.mit.edu/afs/athena/org/m/...ms/paper12.pdf
It's more about using jets spraying onto the die, but tiny ones,
100uM diameter.. They are doing the research though.

Last edited by Starman97; 05-22-2004 at 09:40 PM.
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