Yeah, they thinkin' the same thing I am, just different scales/justifications. The reason behind not connecting the board ground with the parallel port ground is induction, loop = antenna. In the meantime, the parallel port signals are noisy (no reason for the mobo maker to use filter caps on the outputs, in their normal task it doesn't matter). Beyond the loops thing, letting the the signal current return to ground via the parallel port keeps the local ground cleaner.
The latch doesn't need a similar treatment. It's not bothered by noise, and any noise it introduces when activated isn't important since you aren't going to be doing AD conversion at the same time you're setting the latch.
Then again, do I really know and understand the things I think I know and understand? :shrug:
Vias: I've never done the rivet thing, it sounds frightening. Speaking vias, you could kill a number of the ones west ot ADC if you move the Vref line to underneath the ADC (it's DC so it won't be an issue) and remove the reduntant ground connections.
The parallel port has its inputs at the north end and outputs at the south, while you have the digital-in connector to the south and the -out to the north. You could eliminate a couple vias and shorten a lot of traces there.
Ground for U7 and it neighbors is a problem. All the return current from there passes under the ADC; any noise C3 bypasses to ground will travel directly under the ADC.
Diff-Eq, ewww. I went to class three times, don't expect me to decypher that. You should patent that combined PWM/FM concept.
