It used to be in the good old days that power dissipation in CMOS chips increased linearly with clock rate and by the square of the supply voltage. So double the clock rate, double the heat, Double the supply voltage 4 times the heat, Double both and it's 8 times. These relationships still hold but these days with .13 -.09 micron dimensions the leakage currents are very significant and so add another dissipation factor on top of the previous 2 so you can't so easily extrapolate from known dissipations.
Another major factor is that with increased Vcore the gate drive voltage is higher and the on resistance of the devices goes down (which is the whole idea of increasing Vcore to make it run faster) and the totem poles spiking current increases. This is the current where a gate is switching and both N and P devices are briefly on at the same time as they transition and essentially shorting the supply. The totem pole current increases with Vcore. It also increases with the reduction of switch resistance from increasing Vcore which means it goes up even faster than just 1:1 with voltage. And as the devices heat up the turn on thresholds of the transistors decreases so the totem poles now short out for a longer periods of time on each transistion.
What all this means is that increasing Vcore increases dissipation at a very high rate.
Increasing Vcore reduces switch resistance which makes things switch faster which is why we overvolt, but it produces a lot more heat. More heat produces higher temperatures which increase switch resistance which slows things down, which is why we try to cool as much as possible. At some point increasing Vcore produces less speed gain than the increased temperatures reduce the speed.
So use the minimum Vcore possible that will do the job.
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