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Unread 11-21-2005, 02:42 PM   #188
bigben2k
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Join Date: May 2002
Location: Texas, U.S.A.
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Quote:
Originally Posted by unregistered
welcome to the party Ben...
I've arrived!

Ran a quick cal of the 85% uniformity JEDEC requirement; all is well, from a contact area perspective (96% contact over core area, based on 14mm square core).

Quote:
EDIT
it just occured to me,
do you guys understand that the Intel thermal limits are based on the case (IHS) temp ?
I did. Worst case too, which gives us overclockeability.

Quote:
this die temp stuff is not necessary to effective cooling as such is a consideration in package design, for thermal mgmt Intel defines the case temp as the basis of many calcs (AMD grooves the sink so their reference is the other side of the TIM joint, the sink or wb bp - probably a relic of their bare die days)
Agreed, AMD needs to catch up.

Quote:
Originally Posted by Cathar
...
I'm out. Totally.
Ah darn, now I have to pickup Stew's case (no irony, will actually do).

Later today.
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