[Cathar]

Originally Posted by BillA

am I correct in understanding that this is the last leg of your and Stew's claim of misrepresentation against Swiftech ?

Bill. Cut the crap will you? At no stage did I ever claim that Swiftech intentionally misrepresented anything.

I see non-Swiftech reports of similar performance for the 2 wbs with IHS, so I'm thinking the 2 of you may have dropped that line of attack ?

All that was ever said was that there were suspicions that TTV results were inconsistent, and that IHS's are inconsistent.

w/o ever admitting that Swiftech's representations were 'not unreasonable' of course, this is the 'net where one can dump and run

Troll-bait.


Posted at [H]ardOCP, but ignored:

Originally Posted by Cathar

Thing I don't understand is this. The documents linked to by Marci refer to the Tjunction, which by itself would completely satisfy me, and most any overclocker, about the temperature of the CPU/heat die. Tjunction being the temperature positionally located in the middle of the die, located between the die itself, and the CPU packaging substrate. It'd be the next best thing against the most desirable option, which would be having access to TCC readings ( TCC being the on-die thermal probe located within the ALU on P4's).

So with that, it seems that the present Intel supplied testbeds given out for validation purposes do not allow for the measurement of Tjunction. If they did, then in my mind, that would totally absolve any concerns that overclockers have, being that rather than merely knowing the IHS surface temp, we now know what's going on at the die level as well. Sure, we can argue for days about whether or not Tjunction is truly representative of the die temperature, but I can say one thing, it is better than nothing at all.

Having Tjunction, along with Tcase, would allow for at least some quantification of TIM1 in all scenarios. Intel themselves appear to clearly be using Tjunction to perform internal assessments of TIM1 as pressures vary, and since much of the call for TIM1 quantifications seem to be evidenced in geometrical and pressure variations of cooling devices, this would seem to me to be what is needed to solve the issue, and allow testers to quantify TIM1, and allow testers to quantify the die temperature in a more precise sense than merely measuring Tcase, which is itself subject to variations due to wb flatness.

Using Incoherent's flux block method to quantify TIM2, and then we have pretty much all the answers we're after.

So a call for consistency is now to be interpreted as accusing a company of "intentionally misrepresenting"?

To think that some have the gall to claim that others have some hidden agenda.