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Originally Posted by Phoenix32
I am a hardware guy, not software, so our perspectives may come from different angles (engineering tech, R&D).
I will have to say, just for the fun of it, nothing else. You say your experience says timing is not an issue, yet in your own text you hint that timing is realavent.  And for the record here, we are talking PATA here since the subject is older Snap Servers. |
I do both hardware and software... almost entirely UNIX based... (I don't do windows)... Many industries and environments.. (I would be bragging to list them)...
I think things here are a bit more complicated than simple logic can cover, without making a whole laundry list of truisms... Complicated systems can be chaotic.. (If you don't believe that, just look at the evolution of DNS.. worlds largest database administered by thousands of different admins and it still works... sort of...).... and often contradictory conditions can occur... just depends on whether specifications and standard are followed or ignored....
I will admit that timing is an issue, but, in a world where things are supposed to be synchronous... (remember, controller on the drive, not the adapter), there should not be any timing issues. Software needs to wait for acknowledgement from the controller. synchronized spindles did accomplish a near gurantee of simultaneous completion from all elements... (This theory assumes no bad blocks in the target areas.. as seeking to satisfy a block replacement screws everything up)... A parallel to serial (and vice versa) adapter should not, in theory, introduce any delay in signal.... In practice, it may not actually produce delay, but, may produce jitter.... (for those of you who have experience in forwarding synchronous digital circuits may remember what used to be called a tail-circuit.) Jitter means that the edge of the timed pulse may actually occur slightly before or after when it's expected. (as determined by the digital clocking) That and the fact that clocking delay is introduced by wiring length and possibly differing clock frequencies (if the adapter has it's own clock -- it really should not since it's supposed to be a slave, but, I digress even more). This is due to bulk manufacturing tolerances for components used in producing these digital adapters. I still think that any proper design should compensate for these issues, but, therein may be the rub... Proper design often is lacking in our industry... And it's more and more prevalent as time goes on... The only practice that combats this with reasonable efficacy is component matching. These days we have been reduced to matching drive brands, sizes, formatting and firmware. Since this is something that I have practiced as a matter of habit from my early days (when I actually could match resistors and other components when working on my PDP-8's rotating disk storage (DF32/RM08))... I was just laboring under the assumption that everyone knew this... My bad, I guess... Maybe I have been doing high level support for too long....
Thanks for a decent discussion... you have forced me to remember more of what I had allowed to atrophy from disuse... That seems to be what happens after you have been doing this for too long... you seem to forget about stone knives and bearskins....