Thread: Cooler testing
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Unread 10-06-2003, 08:41 PM   #25
winewood
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Join Date: Nov 2002
Location: in my chair
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I understand fully what an NDA is. Am I arguing that hes not forthcoming with information... or the people attempting to derive conclusions from no information!??? Its the LATTER. You guys derive WAY too much from the air here.
Quote:
Intel says there's a temperature difference of up to 8C from one point on the P4 to another. Must we simulate this as well? Your assumption that the LWRR performs significantly worse on an IHS-equipped CPU is based on what
errr.. the information would come directly from .. Cathar. He stated that his block wasn't designed to be used with a TEC and it was.. per his design only to cool the surface the size of the core.
As for the temp diff across the IHS, placing a IHS on a core die sim would come much closer to "simulation" than disregarding it because you guys aren't willing to account for it..
Quote:
adding a I.H.S is like moving the die- Don’t expect current performers to remain such and ignoring the I.H.S in testing is only skewing results.
EXACTLY! is joemac the only one who can see this?? It seems that some past understandings or notions may be controlling judgement a tad more than thought..

But don't let me sound angry.. in any form I am not.. just want testers to accept the environment they are in now. They are afterall testing tomorrow's blocks, not yesterdays...
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Last edited by winewood; 10-06-2003 at 08:47 PM.
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