Die Simulator vs. CPU Article Discussion

[pHaestus]

Article is here

Think of it as a general overview and a launching point for CONSTRUCTIVE discussion on testing please. Any comments, questions, additional information, or clarification should go here.

I hope we can now get all the discussion into this single thread instead of crapping all in every waterblock review thread on the planet k thx.

[BillA]

a cogent survey of the state of testing, Thanks pH

makes sense to me also to consider different test platforms developing data for different purposes
that such platforms would differ in their price/performance objectives would enable testers to evaluate the 'best bang for the buck'
(what info does their audience want, and which platform/methodology is best suited - adaquate ? - to develop that data)

from a testing perspective; there are different uses for data some of which require good accuracy and precision (product design), but others for which lower resolution data is quite sufficient (product performance for example)

the right tool for the right job

[the jew (raven)]

A very thorough and informative article. Props to you.

[GlassMan]

I hope we can now get all the discussion into this single thread instead of crapping all in every waterblock review thread on the planet k thx.

Amen

[pHaestus]

I will try and dig up all the good links and posts made by Marci and others today and compile them here. Eventually I'll get them into the article. I am hoping to get some more discussion than just "you rock pH" up in here too. They are still arguing about whether diodes on P4s are reliable or not in the Apogee thread for example (I'd add a lol if I could bring myself).

[BillA]

I would hope that those arguing about P4s are also those using them, but that issue is outside your article
it would be more proactive if those proposing things also had a specific interest in that type of testing
- IF those comments apply to CPUs in a 775 package, then it is the accessing and intrepertation that is of interest

if you can manage the disparate elements pH, it will help to keep separation between bare CPU, CPU w/IHS, and die sim methods

[bigben2k]

What we need is a demonstration (proof) that the AMD internal TIM is variable.

Intel's internal temp probe is on the edge of the core (and therefore not representative), we know, which makes it a poor temp probe for CPU testing. TCC is not accessible (except as an on/off state). That leaves the IHS groove.

I also believe that the dynamics behind the IHS (Intel or AMD), physically, are a black hole. We could use more info there too.

I'll be pursuing the heat die route, on 10mm by 10mm, as well as 14mm by 14mm, with a floating, grooved, IHS; at least my mounting surface will be durable. I was planning to adapt the heat die to a dead motherboard; I'll see what can be done there.

[BillA]

stacked sensors per Inco ?
(I have extra phenolic if needed)

EDIT
when you say "we", who are you including ?
no, you want it
to me it is a terrific waste of testing time and $ to confirm that over which there is little controversy and to quantify that for which there is no use
perhaps this would be a good tune-up for your bench ?

[gmat]

Isn't the IHS irrelevant anyway ? Who wants to keep this thing in the thermal path.

[BillA]

Intel users ?
- one of pH's proposed 3 ways to heat a wb

[nikhsub1]

Originally Posted by gmat

Isn't the IHS irrelevant anyway ? Who wants to keep this thing in the thermal path.

Look, removing the IHS from a 775 Intel is nearly impossible... that is the bad. The good is, it is a non issue since it is not removeable and the IHS > Core TIM is much more consistant than the AMD's. I have a feeling that AMD will move to soldering the IHS to the core as Intel has done. AMD seems to be about 2-3 years behind in the IHS dept. Trust me if it were as easy to remove as the Northwoods and AMD's mine would be gone.

Note to the 2 thermal diodes agument; I don't see what the fuss is all about really. One diode is for the user to monitor, yes it is in a 'cooler' spot on the core, but an internal reading none the less. The other unreadable diode is only for throttling and thermal shutdown / protection, we ought to consider this diode dead unless it can be read somehow. I am confident (yeah no 'real' proof here) that reading the diode we can read in the P4's would show various WB performance MUCH better than with an AMD and the IHS. If anyone has a block that will fit 775 that they want to loan me that is arguably worse than the G5, I'll be happy to slap it in and record the differences with the basic tools that I've got.

Perhaps testing should move to tying into the P4 readable diode and using the 775 as the testbed for IHS based CPU's as for one, the TIM is far better and 2, it is not removeable. Leave the AMD for IHS-less tests.

[BillA]

"Perhaps testing should move to tying into the P4 readable diode and using the 775 as the testbed for IHS based CPU's as for one, the TIM is far better and 2, it is not removeable. Leave the AMD for IHS-less tests."

reasonable to me
with both bare and clad, W is not known but guesstimated (on basis whatever)
- for bare (AMD only), C is based on pH's diode reader ?
open source ? technical skill req ? cost ? (does procooling care if ph's bench is unique ?)
- for 775s, C is based on the TC reading of the grooved IHS
open source dwg and procedure ? skill ? cost ? (does procooling wish/intend doing 775 based testing ?)
-> why not ? (want more readers ?)

The heat die sim seems more problematical, what now needs to be recognized is that a good die sim is far more than the slug I began with. To derive a non-intrusive face temp requires a sophisticated design with excellent equipment and procedures, a commitment of time and resources. Ice Czar is perhaps the only possibility for such a device that I am aware of, inclined to test commercial products.
peeps wanting a good die sim should be really nice to IC

[nikhsub1]

For 775's C should be based on diode reader and/or TC in grooved IHS, would be nice to see the IHS vs diode data, this is what I've been after ever since I learned of the TTV. We know what TC readings in the IHS already result in, confirmation of it and the relationship of it in re to diode is going to hopefully yeild some 'fun' data.

[BillA]

no Scott, I truly do not understand why experience - the only experience available to you guys - is so casually dismissed
??
again
you do NOT know the IHS temp, properly measured
who has done so ? data ?

I agree it will be interesting to see the comparison.
I would disregard a diode 'reading' if an actual physical measurement is available, but that is only my preference

Does the "diode" temp = the "die" temp ?
Where is this defined, by whom ?
We have a die temp from JoeC (2 or 3 in fact), another from pH, several from Lee; which is the real deal ?
-> What is the target ?

Not trying to be difficult, just pointing out that some decisions need to be made, at least by the tester putting together a bench.
Shall we launch another impossible popularity debate ?

Can we define "die temp" ?
method of measurement ?
different for AMD and Intel ? (why, how to compare ? - sink performance must be predictable)

[Les]

Originally Posted by BillA

...
Does the "diode" temp = the "die" temp ?
Where is this defined, by whom ?
We have a die temp from JoeC (2 or 3 in fact), another from pH, several from Lee; which is the real deal ?
-> What is the target ?.....

"What is the target ?"

My idea of the target is the temperatures associated with attached suggested-power profiles.
My "testing target" would be to characterize these with one temperature measurement.

Going to the pub

[BillA]

all of these are approximations of something else
cannot see any benefit to deriving data from other than the center,
again approximations relating to . . . this rather well undefined 'die temp'
- note that a single (point) masurement will not describe that profile, not a constant

I accept we are not talking about any temp described in a Thermal Design Guide, so where does it come from ?
we have 90°C #s, 130°C, what ? do these numbers relate to something measured ? (by whom, how ?)
we seek a greater range so a 'die temp' is considered better than an IHS temp,
I'm seeking an explanation of the basis for defining, for our purposes, the die temp

[Les]

Yes. all the razor.
At the moment there is nothing on which to use Ockam

[slavik]

Bill, using the center, even though logical, could produce "bad" results. Notice that most CPU designs are not symmetrical and usually have the L1 and L2 cache at one side.

I think the best idea would be to use a die simulator and a real CPU and testing exactly the same waterblocks (trying to keep everything else the same, I know it is difficult) to try and correlate the 2 testing methods where the give consistently the same result.

example: give a CPU that has a power consumption of 100W, use "software heating" (this can range, but has to be the same once a method is chosen, method has to be exact ... a program that is specifically designed to do this, or a program that can be readily monitored/controlled. The said program also can't be based on any multi-user operating systems ... windows,unix,etc.) and then try to vary the power applied to the die simulator that produces the same readings that the CPU does.

In both cases, the temperature probing should be done in the same way ... would it be possible to drill into the IHS and stick a thermal probe in there?

The idea here is to create a simulation which is "close enough" so then you can adapt it to other CPUs and be able to graph out close approximations to how a cooler would act on a given CPU. Thus you get a database, where you choose a cooler (air cooler per say, assuming all come with a fan that isn't changed) that can be tested on a die simulator and then results can be produced with simple calculations ...

I also think that testing should turn to less exact changes ... meaning, I don't care if one cooler performs by 1C better than another (highly subjective) ... I would care though, how they would handle themselves in a variety of ambient temperatures (mainly 20C to 30C in 5C increments, inclusively).

Also, don't forget that until you can measure the kinetic energy of every molecule, no matter how you construct your testbed, you will never produce 100% accurate readings ...

To those lazy to read ... create your own testbeds but find a single standard testbench that you can correlate your tests to. This way, we can compare various results and correlate them between reviewers.

Much like in file formats ... there are Alcahol CD image formats, then there is Nero, then there are a bunch of others ... but the ISO 9660 is standard and anything can be converted to it and from it.

[BillA]

read the P4 TTV inst, follow them in general
this is technology, not science

[Les]

Originally Posted by BillA

...cannot see any benefit to deriving data from other than the center,
again approximations relating to . . . this rather well undefined 'die temp'
- note that a single (point) masurement will not describe that profile, not a constant.......

Yes - "center" are the easiest to model.
Hopefully a judiciously placed temperature sensor and a Total Power(both transmitted along primary(HS) path and Source) can distinguish between four cases shown.
Presently investigating(with Incoherent's [13beermat] ^(3++) simulations) "judiciously placed".

[Brians256]

Bill, you say tech and not science, but I have to play devil's advocate. Some people here are interested in the science and modelling.

Les, thanks for running the numbers to show how a centered power source distributes heat across a 101mm^2 silicon die (I hope I'm reading your graphs correctly). I'm not sure how they can help, though. We don't have a case of even a single hot spot. A P4 die has several potential hot spots that shift as the instruction mix changes.

Would a waterblock do significantly better if it was designed to focus on known hotspots of a particular CPU? Better, meaning better overclock or increased stability (e.g. better stability despite equal or worse/higher temperatures measured at some arbitrary location like the P4 diode)?

[Les]

Originally Posted by Brians256

Les, thanks for running the numbers to show how a centered power source distributes heat across a 101mm^2 silicon die (I hope I'm reading your graphs correctly).

No, you are not understanding correctly.The graphs are illustrative statements of the problem. The graphs are "suggested heat sources" not the distribution.

Originally Posted by Brians256

I'm not sure how they can help, though. We don't have a case of even a single hot spot. A P4 die has several potential hot spots that shift as the instruction mix changes.

Two illustrative HotSpots on the "pkg-face" of the same die are shown (link)
Helps because a statement of the problem is essential to getting a solution.The distribution is part of the solution. The solution is being investigated, starting with an even simpler case than previously illustrated - Uniform Central HotSpot on square 0.5mm thick slice of Si(attachment)

Originally Posted by Brians256

Would a waterblock do significantly better if it was designed to focus on known hotspots of a particular CPU? Better, meaning better overclock or increased stability (e.g. better stability despite equal or worse/higher temperatures measured at some arbitrary location like the P4 diode)?

Dunno, but AMD engineers are giving due consideration("Beware of Hot Spots" Marci's link)

[BillA]

Brian
that the 'scientific' interest exists I agree, but many wishing to opine do not understand the underlying technology

"example: give a CPU that has a power consumption of 100W, use "software heating" (this can range, but has to be the same once a method is chosen, method has to be exact ... a program that is specifically designed to do this, or a program that can be readily monitored/controlled. The said program also can't be based on any multi-user operating systems ... windows,unix,etc.) and then try to vary the power applied to the die simulator that produces the same readings that the CPU does."

I am not interested in the above wishful dream as many here have beaten this topic for 5+ years
deal with what we have first,
then - using that info - define the next useful step

lol
this crowd cannot even measure an IHS temp, or even agree as to its utility
science ??
a way to go yet

[Les]

Originally Posted by Les

]...... The solution is being investigated, starting with an even simpler case than previously illustrated - Uniform Central HotSpot on square 0.5mm thick slice of Si(attachment)...

A snapshot of some of Incoherent's preliminary work.

[Brians256]

What software did Incoherent use for that, again?