The plan for my next week

[Joe]

Originally Posted by BillA

no good reason to waste $ to groove an AMD IHS if the joint is to be considered variable before the fact

Bill I still want to know what basis shows the intel IHS is any less variable than the AMD besides just what some of the vocal AMD folks have said about their CPU's? Relying on hearsay, and rumors in the back corners of the web, isn't that scientific of a basis for thinking the Intel is a superior design than the AMD. (or if there is any real difference at all besides what people report)

Trust me if there was any real factual examples that the Intel in the long term is a superior setup than the AMD I would be cool with it. But as far a I am concerned until then the Intel is as suspect as the AMD is.

Is it possible all the hard core are just using AMD's resulting in more vocal people using them, and therefore more vocal people complaining about them. If a small fraction use Intel CPU's then complaints about IHS variability will be less also.

[BillA]

any data is better than no data, we can always argue about what it means
lol

how could the IHS+TIM joint be an offset ?
not and be modeled as resistors, eh ?
the IHS has conduction losses and the TIM joint the 'variable' C/W so much discussed

would it not be: die size wrt the 'effective area' of the wb ?
an interesting analysis indeed

[nikhsub1]

Originally Posted by Joe

Bill I still want to know what basis shows the intel IHS is any less variable than the AMD besides just what some of the vocal AMD folks have said about their CPU's?

Let me explain. The 775 Intels IHS's are somehow BONDED to the core, either with epoxy thermal adheisive or some sort of solder. It is NOT easy to get the IHS off, in fact I won't do it anymore. I have cut the epoxy 'ring' round the outside of the IHS which used to remove the IHS on the Northwoods (and current AMD's) but not on the new Intel's. In fact, I posted how I stuck the CPU in the oven at 400 f for an hour, froze the thing overnight, even soaked the damn thing in googone and the IHS still would not come off. Consider Intel's IHS to core a permanent bond if you will.

Now, my thinking here in re to IHS testing and IHS-less testing. If pH were to use 2 different CPU's, one with and one without IHS I think this would be fine. My thought is that the tests with the IHS will numb the cooling affect of all blocks, just like Lee's CPU test did. I think from a Maze 3 to an Apogee to a Storm the IHS based test will yeild each block within 1C of each other (On an AMD IHS that is). With the IHS removed, all bets are off and there will be no doubt which block will perfrom the best. The Maze 3 will show exactly what a dog it is as well.

[BillA]

Joe
I have no absolute knowledge re internal TIM joint variability or reliability, I 'know' no more than I hear
IF I hear of no problems (imperfect listening, I know), I will consider that no problems exist
I have no difficulty with hypothetical questions, and wonder when such questions are refused consideration

some very toasty chips are in 775 packages, anyone know of TIM joint 'problems' with that package ?

[nikhsub1]

Originally Posted by BillA

some very toasty chips are in 775 packages, anyone know of TIM joint 'problems' with that package ?

None. Read up one

[bigben2k]

Keep it simple.

[BillA]

Originally Posted by nikhsub1

None. Read up one

whew Scott, you just impaled Stew's whole case
why did you not dissent when Stew stated that ALL IHS clad CPUs had a variable TIM joint ?

do you understand the testing implications of a 'sound' internal TIM joint ? (however 'sound' is defined)
now how about a 'sound AND consistent' TIM joint ? (don't get upset, a hypothesis eh ?)

[Albigger]

Originally Posted by bigben2k

Keep it simple.

Agreed. This has gotten very big very fast.

pH: answered my questions, thanks. IF you want to explore the IHS to CPU joint:

Originally Posted by pHaestus

The dT CPU-water is the same for the same wb at the same flow rate and at the same vcore/FSB/multi on multiple chips. Since I did the calibration of the whole soldered up system described before.

This is good info, shows consistency and that in fact, on bare die cpus the heat output may actually be fairly consistent.

And YES if CPU temps go down then C/W would decrease. How much though? Is this a constant change (an offset) for all wbs, or do some cool the IHS or die area in a way that makes them particularly affected by the change? THIS is a good question I think.

IF you think its a good question (and many others here do also) then may be worth exploring. The decrease in C/W, in general, has no reason to be a constant offset. Issues:
1) The internal geometries of the waterblock probably has an optimum C/W for a specific heating area (die size) - the effect may not be too large (for example on pin-array blocks) but may be more pronounced on concentrated cooling blocks. This (in my mind) can never be generalized as an offset, only found by a) testing each waterblock on different die sizes / die sims or b) computational fluid dynamics / other modeling
2) The IHS joint, IF variable, will introduce varying amounts of resistance to the heat path, thus on different processors the heat will diffuse more than others in the IHS, and present a larger effecting heating area to the waterblock on some cpus, and of course it will diffuse large heat flux gradients and appear a more uniform distribution.
3) the IHS joint degrades over time. I don't find this particularly interesting, and would think you would have to pick one cpu and test with one standard block over multiple heat and mounting cycles.

My take is that 1) is probably negligible for 'small' changes in die area (wrt the original die size) and can probably be logically estimated once we have some examples. I would much like to characterize 2). IF it is found that the IHS joint IS consistent, then the modeling (I believe) can portray it as just an offset (temperature) from the core. IF it is found not consistent, the best we can do is provide an 'average' offset with statistics (requires testing more cpus).

Sorry for the long-windedness. pH if you are serious about characterizing the IHS joint as I said earlier, I THINK it would be enough that if you saw uniform temp drops (NOT WITH EVERY BLOCK) but with the same block on multiple cpus after removing the IHS then you could say it is consistent. If you want to be more thorough grooving the IHS is an option and then provides a verification method.
Scenario:
1) IHS is constant/consistent. calibrated Thermocouple in grooved IHS is a constant offset (on all cpus with same cooling method) from calibrated thermocouple soldered to cpu pins. When removing IHS the temperature drop associated with a specific waterblock is the same across all cpus.
2) variable IHS - neither dT(IHS topside - core) or the temp. drop across cpus is consistent.

I may be able to groove the IHS top if you need, if this is the route you decide to go with (but would have to know the requirements before I could say for sure).

[Marci]

For reference, Intel uses Indium Solder for it's TIM1 joint (die to IHS) in current gen cpus - http://www.enerdynesolutions.com/lea...nterfaces.html << last paragraph - only public source I can find to quote... but it's fact.

http://www.intel.com/technology/itj/...linterface.htm
That's the 2005 uptodate document on their current research into the gels they intend to use to replace it... (Look into Low Melt Alloys and Indium Solder and you'll find longterm reliability issues that may or may not have been addressed... but Indium isn't up to the job longterm... especially when working at -55 deg C temps - phasechange crowd beware... see AMD link below for some projections of when phasechange Direct Die projectedly becomes necessary.)

Also recommend http://www.intel.com/technology/itj/...ol09_art03.pdf
Bookmark: http://www.intel.com/technology/itj/index.htm if u ain't already and keep an eye on it for newer info...

Some info on page 9 onwards for AMD CPUs TIM1 here, as well as hints of trouble ahead: http://www.apialliance.com/pdf/Archi...Touzelbaev.pdf

[nikhsub1]

Originally Posted by BillA

whew Scott, you just impaled Stew's whole case
why did you not dissent when Stew stated that ALL IHS clad CPUs had a variable TIM joint ?

do you understand the testing implications of a 'sound' internal TIM joint ? (however 'sound' is defined)
now how about a 'sound AND consistent' TIM joint ? (don't get upset, a hypothesis eh ?)

No I don't think I impaled anything... It is still possible for a block to flex on the IHS pulling the center convex, away from the heatsource which would yeild 'funny' results...

[Les]

Marci, good links
Ta

[pHaestus]

So I should get crackin' right?

Here's the order of business as I see it.

1) Test Swiftech Storm, some old low performance wb, and my Cooltechnica WW LE and write a review up.
2) Get an AMD64 compatible Swiftech MCW6000 and Apogee, test them, and post review.
3) Remove IHS from my 3000+ and repeat tests of all these blocks. Give data that YOU guys want to see at this point. Revise the above reviews to contain IHS and bare die numbers.

Seem reasonable? Any modifications you would require?

[Joe]

I would say you are good to go but in the other thread there is from others that the Intel 775 solution is the way to go. (Which since neither of us have one thats not really likely to happen)

To me I would say go with what you have listed and be merry.

[BillA]

Joe
different things in different directions
the 775 is only relevant to 'as bought' CPU based testing as the IHS cannot be removed - hence the (presumed) difference between it and the AMD products

any comparative IHS testing must be with AMD CPUs

pH
and dP ?

[pHaestus]

At the moment I cannot produce dP vs. Q curves. I don't honestly want to fiddle with my xmitter any more because every time I do I lose a day and then get frustrated and just quit.

If only there were someone who could supply dP v. Q curves for a wide range of waterblocks...

[BillA]

gotta be a 'trusted source' though, can you vet ?
need to cross-correlate flow with some precision

[bigben2k]

Originally Posted by pHaestus

...If only there were someone who could supply dP v. Q curves for a wide range of waterblocks...

I just picked up a Rosemount 2024, cal'ed 0 to 250 inH2O. (Bill: he's local to us, ever closer to you than me, and offers recals).

Output is 1-5 volt (not the usual 4-20 mA). Since I won't be using it right away, I can loan it to you, for a few weeks.

[billbartuska]

Originally Posted by Brians256

Could we try some tests before and after IHS removal? Also, if you have a really low end block to compare with the known good blocks, that would be nice.

Like a Maze4.

[Les]

Deleted
Was info request.Now too late.Moved on

[pHaestus]

hmm we have multiple threads AGAIN about IHS. It seems like the forum waffles back and forth daily on the subject.

[BillA]

threads ??
hell, across the forums, blame Marci
http://www.hardforum.com/showthread.php?t=988998
http://www.hardforum.com/showthread.php?t=989089

[Marci]

/me presents face for gag installation...

[Les]

Originally Posted by Marci

...Some info on page 9 onwards for AMD CPUs TIM1 here, as well as hints of trouble ahead: http://www.apialliance.com/pdf/Archi...Touzelbaev.pdf

Yes, am finding some useful info in links.

Concur with AMD's "Die Thinning: Beware of Hot Spots".
For "at-the-die-surface heat flux cone diameters"< ~5mm, modelling suggests TIM(0.06c/w per cm^2) rules( (contributes>50% of Resistance) for all wbs
Would add. a bit of edge cooling could work wonders : Modelling suggests a highly potent effect of ,say, a 150w/m^2K(forced air in 0.5mm gap) side "Heat Transfer Coefficient" in reducing a spike a hundredfold ,given of course there is a dT to cool.

Edit: Anyone know undercup bp thickness of the Storm G4 ?
Have upped from 0.7625mm to 1.2625mm following Cathar's "Storm's bp is substantially thicker than 1mm" (link to page).
Is this right?

[pHaestus]

God my head hurts and not from drinking (this time).

So what do the experts suggest that I do? Testing with IHS seems impossible on AMD, and testing Intel CPUs seems like a pretty large cash investment and will leave me with ONLY CPU case temps. Die sims are not esp attractive to me as I really like the chance to evaluate mounting issues and cooling of real CPUs.

Sometimes I think I should just stick with the damn Socket A CPU and avoid all of this!

[BillA]

2 paths; CPU and die sim
CPU bare
CPU w/IHS

die sim
(die sim + IHS ??)

clearly AMD bare die testing is highly relevant to the 'enthusiast' community, test that way and be done with it
- for those so concerned such results could be correlated (with a sack of salt) to other setups

given the presumed fragility of the AMD Tim1, it is not worth grooving so at best you could get a dT across it and some other stuff, ??

when and if the CPU w/IHS discussion evolves to some nominal agreement, AND interest, then you could consider jumping through your ear backwards

can't please all, especially here