Copper cap for AMD processor?

[bigben2k]

Dunno if it's available state-side...but here it is.

In short, it's a copper shim with a twist: a copper sheet over the core.

It'll increase your core temps only 1 or 2 deg C.

Would you use it?

[pHaestus]

Not I

[Puzzdre]

Me neither...I don't like the idea of more layers over the core, no matter how brittle it is...

[Brians256]

Likely the manufacturers will probably start using them though. Safety and reliability is more important than performance to a manufacturer.

[joemac]

I was thinking the same thing Brians256 – wonder what is taking AMD so long though. Maybe it is a good thing that they have not what if they cover the bridges with the cap. Then I would have to take it off - OH NO...

[Pritorian]

He he, yeah.

now that would not make life so easy anymore.

It´s really the only reasone after price to get an AMD chip now a days.

-P-

[pHaestus]

For me, having a bunch of Socket A mobos and coolers around is the reason to buy AMD. Nothing more atm.

[BillA]

a more correct description of that test is that their indicated temp changed 1 - 2°C

makes no sense at all, their first temps were more realistic
too many variables

but think on it:
if the TIM joint = a temp OFFSET of x°
then 2 TIM joints cannot be less than 2*x°, plus the conductance resistance of the shim's thickness

heating up air pockets ??
vs. gobs of grease ??? -> lower temps ?????

sh*t, can't anybody THINK ?

[pHaestus]

Bill: Abit mobo (nforce2) means most likely an in-socket thermistor.

[BillA]

no difference with their index finger at 98.8

its deductive reasoning that's lacking

[Les]

Originally posted by unregistered


if the TIM joint = a temp OFFSET of x°
then 2 TIM joints cannot be less than 2*x°, plus the conductance resistance of the shim's thickness

I suggest it can .
Perhaps the considering as a "Finite Compound Spreading Resistance"* problem and comparing to the "Finite Isotropic" case** may give some insight.Maybe the "isoflux" is questionable but ....
An example of the "Compound" case for a 40x40mm heatsink with a 1mm Cu heatspreader :

comparing to the "Isotropic" case get:


However this only suggests that the heatspreader may have minimal detrimental effects with cooling which is poor in the first place.

* http://www.mhtl.uwaterloo.ca/old/onl...ce/strip1.html
** http://www.mhtl.uwaterloo.ca/old/onl...ce/strip2.html

[BillA]

Les
you will persist in making me think, eh ?

I think your compound model is missing a layer
the source 'q' with it's dimensions - fine
'Layer 1' would be the 1st grease layer
'Layer 2' would be the Copper Cap shim proper

-> a 'Layer 3' is needed for the 2ed grease layer between the Copper Cap and the hsf (or wb), no ?

some questions come to mind re the Compound Channel model . .
as I understand the theory/practice: a thermal offset will be present between 2 discontinous pieces even if swedged under 'perfect' conditions
- perhaps/hopefully small, but still existant

what am I missing here ?
I can see where the 2ed thermal offset would be incrementally smaller than the first due to the slightly lower frontside temp
(so my 2*x is not strictly true, no problem)

[bigben2k]

Not to throw this off-topic too much, but how's the P4 heatspreader bonded to the die?

[BillA]

'frag tape' I understand (no personal exp)

[Les]

Originally posted by unregistered
Les
you will persist in making me think, eh ?

I think your compound model is missing a layer
the source 'q' with it's dimensions - fine
'Layer 1' would be the 1st grease layer
'Layer 2' would be the Copper Cap shim proper

-> a 'Layer 3' is needed for the 2ed grease layer between the Copper Cap and the hsf (or wb), no ?

some questions come to mind re the Compound Channel model . .
as I understand the theory/practice: a thermal offset will be present between 2 discontinous pieces even if swedged under 'perfect' conditions
- perhaps/hopefully small, but still existant

what am I missing here ?
I can see where the 2ed thermal offset would be incrementally smaller than the first due to the slightly lower frontside temp
(so my 2*x is not strictly true, no problem)

"Layer 1" is missiing, for which I would just add 0.1c/w( 10x10x01mm at 10W/m*m*m ) as per drift of discussion on "TIM joint "C/W" testing" ( http://forums.overclockers.com.au/sh...threadid=67401 ).
I do not think this effects the trend illustated.
Was only drawing attention,yet again, to the possible importance of "spreading resistance".The current trend in wb design seems to me to be disregarding it.
I also have no problem.